Semiconductor Device Manufacturing Using Selective SiGe Epitaxy
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Solution Overview
Problem
Conventional semiconductor device manufacturing processes for high voltage devices require increased photo masks and additional wet etching and cleaning processes, leading to higher costs and complexity, especially when integrating silicon germanium (SiGe) layers for improved chip density.
Innovation Solution
A method of manufacturing semiconductor devices with embedded high voltage components by preparing a semiconductor substrate with distinct voltage device portions, forming gate insulating layers, and using epitaxial growth of SiGe layers to reduce manufacturing costs and enhance device characteristics, including the use of medium temperature oxide processes and silicon nitride layers for masking and etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SiGe layer is formed on channel region of low voltage device while high voltage device is embedded, then chip density is increased, but manufacturing cost increases due to increased photo masks and additional wet etching and cleaning processes
Solution Approach 1:
The patent applies local quality by forming SiGe layer selectively only in the channel region of low voltage devices, while high voltage devices maintain their original structure without SiGe layer. This is achieved through selective gate insulating layer removal and targeted SiGe deposition, increasing chip density in specific areas without requiring additional photo masks for overall structural differentiation.
Solution Approach 2:
The gate insulating layer serves multiple functions: as a protective layer during SiGe formation, as a mask for selective SiGe deposition, and as a structural component for high voltage devices. By removing it selectively, the patent enables the same layer to facilitate both low voltage device enhancement and high voltage device integration without additional manufacturing steps.
2Reliability
If SiGe layer is formed on channel region of low voltage device, then device characteristic is improved, but process complexity increases due to additional wet etching and cleaning processes
Solution Approach 1:
The patent extracts the gate insulating layer selectively from low voltage device channel regions before SiGe formation. This extraction creates a clean surface for SiGe deposition while maintaining the gate insulating layer on high voltage devices, thereby improving device characteristics through SiGe integration without requiring additional cleaning processes.
Solution Approach 2:
The gate insulating layer is removed in advance before SiGe layer formation, preparing the surface for direct SiGe deposition. This preliminary action eliminates the need for additional cleaning steps after SiGe formation, reducing process complexity while ensuring proper SiGe adhesion and crystal structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and improves device characteristics by optimizing the integration of high voltage components within semiconductor devices, allowing for more efficient and cost-effective production while maintaining or improving performance.
Implementation Method 1
a wet etching process may be performed to remove the first gate insulating layer
Implementation Method 2
the forming of the first semiconductor layer may include epitaxially growing a material having a different lattice constant from that of the semiconductor substrate
Implementation Method 3
the first gate insulating layer may be formed by a medium temperature oxide (MTO) process
Data Source
AI summary
A method of manufacturing a semiconductor device includes preparing a semiconductor substrate having a first and a second voltage device portion, each including a first and a second conductive type MOS region, forming a first gate insulating layer on the first and the second voltage device portion, removing the first gate insulating layer from the first conductive type MOS region of the first voltage device portion to expose a part of the semiconductor substrate, forming a first semiconductor layer on the first conductive type MOS region of the first voltage device portion, and removing the first gate insulating layer from the second conductive type MOS region of the first voltage device portion to expose a part of the semiconductor substrate.