Semiconductor Device Signal Compression for Flip-Flop Reduction
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Solution Overview
Problem
The existing semiconductor devices with dual-core lockstep systems require a large number of flip-flops for signal delay and comparison, leading to increased circuit area and power consumption when comparing n-bit output signals from two processors.
Innovation Solution
A semiconductor device configuration that compresses n-bit output signals into m-bit signals, reducing the number of flip-flops needed for delay circuits and allowing for bit-wise comparison, thereby reducing circuit area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If n-bit output signals from two processors are compared directly using delay circuits, then fault detection accuracy is maintained, but the number of flip-flops increases leading to larger circuit area and higher power consumption
Solution Approach 1:
The patent extracts only the essential comparison function from the full n-bit signal and processes only the necessary bits through compression. By using compression circuits to reduce n-bit signals to m-bit signals (where m < n), the system compares only the compressed essential information, thereby reducing the number of flip-flops needed while maintaining fault detection capability.
Solution Approach 2:
The patent changes the parameter of signal bit-width from n-bits to m-bits through compression circuits. This parameter transformation allows the same fault detection function to be achieved with fewer resources. The compression circuits transform the n-bit output signals into compressed m-bit signals, reducing the resource requirements for subsequent delay and comparison operations.
2Reliability
If n-bit output signals from two processors are compared directly using delay circuits, then fault detection accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent extracts only the essential comparison function from the full n-bit signal and processes only the necessary bits through compression. By using compression circuits to reduce n-bit signals to m-bit signals (where m < n), the system compares only the compressed essential information, thereby reducing the number of flip-flops needed while maintaining fault detection capability.
Solution Approach 2:
The patent changes the parameter of signal bit-width from n-bits to m-bits through compression circuits. This parameter transformation allows the same fault detection function to be achieved with fewer resources. The compression circuits transform the n-bit output signals into compressed m-bit signals, reducing the resource requirements for subsequent delay and comparison operations.
3Area of stationary object
If compression circuits are introduced to reduce bit width, then circuit area and power consumption are reduced, but additional circuit components are added
Solution Approach 1:
The patent merges the compression function with the existing delay circuit structure. The compression circuits are integrated into the delay circuit path, combining multiple functions (compression and delay) into a unified structure. This merging approach reduces the overall number of separate components while achieving the desired bit-width reduction and resource savings.
Data Source
AI summary
A semiconductor device comprising: a first processor; a second processor; a first delay circuit delaying a signal input into the first processor by a predefined number of cycles and inputting the signal into the second processor; a first compression circuit compressing a signal of n-bit width from the first processor into a signal of m-bit width (m<n) and outputting the signal of m-bit width; a second compression circuit compressing a signal of n-bit width from the second processor into a signal of m-bit width and outputting the signal of m-bit width; a second delay circuit delaying the signal from the first compressor by the predefined number of cycles and outputting the delayed signal; and a coincidence comparison circuit comparing bit-wise the corresponding bits of the signals from the second delay circuit and from the second compression circuit to check whether the corresponding bits coincide with each other or not.