Semiconductor Package Signal Routing via Offset Solder Bumps
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Solution Overview
Problem
Conventional semiconductor device packages with face-to-face arrangements of two semiconductor dice require additional processing steps and costs for forming redistribution layers or through-silicon vias to enable proper signal routing, which increases time and expense.
Innovation Solution
The semiconductor device packages are designed with bond pads and solder bumps positioned along centerlines and laterally offset from centerlines, allowing for unique electrical interaction without the need for separate redistribution layers on each die, enabling the same circuitry layout for both dice and facilitating signal routing through conductive solder bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redistribution layers or through-silicon vias are formed to enable proper signal routing in face-to-face semiconductor dice arrangements, then electrical connectivity between dice is achieved, but processing time and manufacturing cost increase
Solution Approach 1:
The patent extracts the signal routing function from the semiconductor dice themselves and relocates it to the substrate level. By positioning bond pads along centerlines and laterally offset from centerlines on the substrate, the need for complex redistribution layers or through-silicon vias in the dice is eliminated, directly reducing processing time while maintaining electrical connectivity
Solution Approach 2:
The patent moves the signal routing functionality from the vertical dimension (within the dice through TSVs or RDLs) to the lateral dimension (on the substrate plane). Bond pads are arranged in specific lateral patterns that enable signal routing without requiring vertical penetration or additional layers within the dice, thus reducing processing complexity and time
2Reliability
If redistribution layers or through-silicon vias are formed to enable proper signal routing, then electrical connectivity between dice is achieved, but manufacturing cost increases
Solution Approach 1:
The patent extracts the signal routing function from the expensive semiconductor dice fabrication process and relocates it to the substrate assembly process. By forming bond pads directly on the substrate in predetermined patterns, the need for additional costly processing steps (RDL formation, TSV etching and filling) is eliminated, directly reducing manufacturing cost while achieving the same electrical connectivity
Solution Approach 2:
The substrate is designed to self-route signals through its bond pad arrangement. The bond pads positioned along centerlines and laterally offset from centerlines automatically provide the necessary signal paths when dice are mounted in the specified orientation, eliminating the need for additional routing structures and reducing overall manufacturing complexity and cost
3Reliability
If unique circuitry layouts are formed on each semiconductor die to accommodate signal routing, then proper electrical connection is achieved, but device complexity increases
Solution Approach 1:
The patent makes the substrate serve multiple functions: it provides mechanical support, electrical connection, and signal routing. The bond pads on the substrate universally handle all signal routing needs for multiple dice, allowing each die to maintain a simple, identical circuitry layout while the substrate adapts to provide the necessary connection complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for efficient and cost-effective signal routing between semiconductor dice without the need for additional processing steps, enabling simultaneous and separate signal transmission while maintaining the same circuitry layout for both dice.
Implementation Method 1
conductive solder bumps that are aligned with and that physically and electrically couple the bond pads along the centerline of the first semiconductor die to the bond pads along the centerline of the second semiconductor die
Data Source
AI summary
Semiconductor device packages include first and second semiconductor dice in a facing relationship. At least one group of solder bumps is substantially along a centerline between the semiconductor dice and operably coupled with integrated circuitry of the first and second semiconductor dice. Another group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the first semiconductor die. A further group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the second semiconductor die. Methods of forming semiconductor device packages include aligning first and second semiconductor dice with active surfaces facing each other, the first and second semiconductor dice each including bond pads along a centerline thereof and additional bond pads laterally offset from the centerline thereof.