Semiconductor Signal Selection Units for Parallel Bit Test Accuracy
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Solution Overview
Problem
Existing parallel bit test (PBT) methods for semiconductor devices face challenges in accurately measuring parameters like RAS to CAS delay time 'tRCD' due to additional sequences required for channel selection, leading to measurement inaccuracies and potential issues in subsequent tests.
Innovation Solution
A semiconductor device with signal selection units that allow for both common and individual test modes, enabling precise control of test signals and eliminating the need for additional sequences during parameter measurement by enabling/disabling specific test signals based on operation modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel bit test is performed by simultaneously selecting multiple channels, then test speed is improved, but measurement precision of parameters like tRCD deteriorates due to additional sequences required for channel selection
Solution Approach 1:
The patent implements dynamic switching between common test mode and individual test mode through signal selection units. The system dynamically adjusts the test configuration based on the specific measurement requirements, allowing seamless transition between parallel testing (for speed) and sequential testing (for precision) without manual intervention or additional sequence overhead.
Solution Approach 2:
The patent segments the test control into two distinct modes: common test mode for simultaneous multi-channel testing and individual test mode for parameter-specific measurements. This segmentation allows the system to optimize for either speed or precision depending on the testing phase, eliminating the need for additional channel selection sequences during parameter measurement.
2Measurement precision
If additional sequences are applied for measuring RAS to CAS delay time during PBT, then measurement capability is improved, but loss of time increases
Solution Approach 1:
The patent prepares the signal selection units in advance to be in the individual test mode when parameter measurement is required. This preliminary configuration eliminates the need for additional channel selection sequences during the actual measurement, as the system is already positioned to perform the measurement directly without time-consuming mode switching or sequence additions.
3Productivity
If common test mode is used for parallel bit test, then test efficiency is improved, but reliability of parameter measurement deteriorates due to inability to correctly measure parameters
Solution Approach 1:
The signal selection units are designed with multi-functionality to handle both common test mode operations and individual parameter measurement operations. This universal design allows the same hardware infrastructure to support both high-efficiency parallel testing and reliable parameter measurement by simply changing the operational mode through control signals, without requiring separate dedicated circuits for each function.
Data Source
AI summary
A semiconductor device includes a plurality of memory chips and a plurality of signal selection units respectively corresponding to the plurality of memory chips, and suitable for commonly transferring test data signals from an external to a corresponding one of the plurality of memory chips during a common test mode, wherein one or more of the plurality of signal selection units may transfer the test data signals from the external to corresponding ones of the plurality of memory chips during an individual test mode, and wherein the semiconductor device may be set to the common test mode when a common test signal is enabled, and set to the individual test mode when both the common test signal and a test control signal are enabled.