Semiconductor Device Silicidation Leakage Current Suppression
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Solution Overview
Problem
The formation of spikes during silicidation in semiconductor devices with SiGe or SiC layers leads to leakage currents and short circuits, complicating the optimization of silicidation conditions, especially when both stressed and unstressed transistors are processed simultaneously.
Innovation Solution
A semiconductor device structure where the semiconductor layer creating stress in the channel region is formed apart from the isolation region, preventing spike formation and allowing for controlled silicidation to suppress leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If silicidation is performed to reduce source and drain resistance, then resistance is reduced, but leakage current increases due to spike formation
Solution Approach 1:
The patent divides the semiconductor layer into multiple regions: a first region in contact with the isolation region and a second region apart from the isolation region. The silicidation process is selectively applied to different regions, with the second region undergoing silicidation to reduce resistance while the first region is protected to prevent spike formation and leakage current.
Solution Approach 2:
Different regions of the semiconductor layer are given different treatments: the first region maintains its original properties to prevent harmful spikes, while the second region undergoes silicidation to reduce resistance. This local differentiation allows simultaneous optimization of both resistance and leakage current characteristics.
2Speed
If SiGe layer is formed to create compressive stress and improve hole mobility, then carrier mobility is improved, but spike formation occurs during subsequent silicidation
Solution Approach 1:
The SiGe layer is segmented into regions with different functions: one region maintains contact with the isolation region to provide stress while preventing spike formation, and another region is positioned apart from the isolation region to undergo controlled silicidation for resistance reduction without harmful spike generation.
Solution Approach 2:
The patent applies different properties to different parts of the SiGe layer: the portion near the isolation region maintains lattice mismatch properties for stress generation, while the portion apart from the isolation region is modified through silicidation to reduce resistance without causing spikes.
3Stress or pressure
If semiconductor layer is positioned close to isolation region for stress effect, then stress is maximized, but leakage current increases due to spike formation
Solution Approach 1:
The semiconductor layer is divided into functional segments: a first region positioned near the isolation region to provide stress through lattice mismatch, and a second region positioned apart from the isolation region to undergo silicidation for resistance reduction without spike formation.
Solution Approach 2:
Different regions of the semiconductor layer are assigned different characteristics: the first region maintains original properties for stress generation, while the second region receives silicidation treatment to reduce resistance without causing harmful spikes at the isolation interface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses leakage currents and ensures high yield and reliability by maintaining sufficient stress in the channel region while preventing spike formation, thus enhancing the performance and power efficiency of semiconductor devices.
Implementation Method 1
Carrier mobility can be improved by using this stress technique
Implementation Method 2
a silicon germanium (SiGe) layer which differs from the Si substrate in lattice constant
Implementation Method 3
nickel silicide or cobalt silicide is formed in a pMOS transistor
Data Source
AI summary
A method for fabricating a semiconductor device to which a stress technique is applied and in which a leakage current caused by silicidation can be suppressed. The method includes forming an isolation region in a semiconductor substrate; forming a gate electrode over an element region defined by the isolation region formed in the semiconductor substrate; and forming a semiconductor lager in the element region at both sides of the gate electrode apart from at least part of the isolation region. By doing so, the formation of a spike near the isolation region is suppressed even if a silicide layer is formed. Accordingly, a leakage current caused by such a spike can be suppressed.