Semiconductor Device Metal Silicide Formation Blocking Ions

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Solution Overview

Problem

Existing methods for fabricating semiconductor devices with N-type and P-type MOS transistors are complex and require improvement to achieve optimal Schottky barriers, as they involve different metal silicide materials and processes that complicate the manufacturing process.

Innovation Solution

A method involving a base substrate with distinct doped regions, where a first metal layer and a second metal layer, made of different materials, react with surface materials to form metal silicide layers, with blocking ions in the second doped region preventing diffusion of atoms from the second metal layer into the second silicide layer, simplifying the process by forming both silicide layers in a single annealing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If different metal silicide materials are used for N-type and P-type MOS transistors to achieve optimal Schottky barriers, then the electrical performance is improved, but the fabrication process complexity increases

Engineering Contradiction:
Improveelectrical performanceVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the semiconductor device into distinct first and second regions corresponding to N-type and P-type MOS transistors. Each region receives targeted ion implantation (blocking ions in the second region) and forms different metal silicide layers through selective diffusion control, allowing optimized electrical performance for each transistor type while managing process complexity through regional differentiation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by doping the second region with blocking ions to prevent metal atom diffusion, while leaving the first region undoped or differently doped. This creates locally optimized conditions: the first region forms a first metal silicide layer with specific properties for N-type transistors, and the second region forms a second metal silicide layer with different properties for P-type transistors, achieving optimal Schottky barriers for each device type.

Inventive Principle:
Principle #3Local quality

2Reliability

If separate fabrication processes are used for forming metal silicide layers in N-type and P-type MOS transistors, then the Schottky barrier optimization is achieved, but the manufacturing efficiency decreases

Engineering Contradiction:
ImproveSchottky barrier optimizationVSAvoidmanufacturing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges the fabrication processes for N-type and P-type MOS transistors into a single integrated process. Both regions receive ion implantation and metal layer deposition simultaneously, followed by a unified annealing treatment that forms both metal silicide layers in one thermal processing step. The blocking ions in the second region selectively prevent diffusion only where needed, allowing both transistor types to achieve optimized Schottky barriers through a combined process rather than separate sequential processes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary ion implantation of blocking ions into the second region before forming the metal layers. This preliminary action prepares the second region to selectively prevent metal atom diffusion during the subsequent annealing process, ensuring that the second metal silicide layer forms with the desired properties while the first metal silicide layer forms differently in the first region, all within a unified fabrication sequence.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If metal layers are formed on both doped regions and annealed together, then the fabrication process is simplified, but diffusion control becomes more difficult

Engineering Contradiction:
Improvefabrication process simplificationVSAvoiddiffusion control
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent introduces blocking ions as an intermediary substance in the second doped region that mediates the diffusion process during annealing. These blocking ions act as a diffusion barrier, preventing metal atoms from the second metal layer from diffusing into the second metal silicide layer, while allowing controlled diffusion in the first region. This intermediary mechanism enables simplified unified processing while maintaining precise diffusion control through the blocking ion concentration and distribution.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent utilizes parameter changes by varying the blocking ion concentration in the second doped region to control diffusion characteristics. By adjusting the blocking ion dose and energy during ion implantation, the diffusion barrier strength is precisely controlled, enabling the second metal silicide layer to form with specific properties while preventing unwanted diffusion. This parameter control allows unified annealing processing to achieve different diffusion outcomes in different regions.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the fabrication process while achieving low Schottky barriers for both N-type and P-type transistors, enhancing their electrical performance by ensuring the material of one silicide layer is not affected by the other, thus improving manufacturing efficiency and transistor performance.

Implementation Method 1

The first metal layer and the second metal layer on the first doped region react with a surface material of the first doped region to form the first metal silicide layer. The first metal layer on the second doped region reacts with a surface material of the second doped region to form the second metal silicide layer

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 2

forming a first metal silicide layer and a second metal silicide layer by performing an annealing process

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 3

The blocking ions block atoms of the second metal layer from diffusing into the second metal silicide layer

Methodology Applied
Scientific EffectIon blocking: Diffusion Barrier

Data Source

PatentUS10297509B2Semiconductor device and fabrication method thereof
Publication Date: 2019.05.21 SEMICON MFG INT (SHANGHAI) CORP
  • US10297509B2 patent drawing
  • US10297509B2 patent drawing
  • US10297509B2 patent drawing

AI summary

A semiconductor device and a method for fabricating the semiconductor device are provided. The method includes providing a base substrate including a first region and a second region; and forming a first doped region in the first region, and a second doped region in the second region. The second doped region is doped with blocking ions. The method also includes forming a first metal layer on a surface of the first doped region and on a surface of the second doped region; and forming a second metal layer on a surface of the first metal layer. The second metal layer is made of a material different from the first metal layer. Further, the method includes forming a first metal silicide layer and a second metal silicide layer by performing an annealing process. The blocking ions block atoms of the second metal layer from diffusing into the second metal silicide layer.