Semiconductor Gate Protection via Silicide Layer Formation
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Solution Overview
Problem
Highly integrated semiconductor devices face challenges with increased contact resistance and sheet resistance due to reduced gate electrode width and contact area, leading to lower operating speeds and potential damage during the salicide process, especially with misalignment issues.
Innovation Solution
The method involves forming a silicide layer on the source/drain region before creating a contact hole, using a sequence of insulation layers to protect the gate electrode and facilitate uniform deposition, and maintaining a low aspect ratio between the gate and source/drain regions to reduce the risk of damage during the salicide process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate electrode width is reduced to achieve high integration, then the device density is improved, but the contact resistance and sheet resistance increase
Solution Approach 1:
A silicide layer is formed on the source/drain regions before the metal gate deposition step. This preliminary formation of low-resistance silicide contacts allows the gate electrode to have reduced width for high integration while maintaining low contact resistance through the pre-formed silicide layer that will be in direct contact with the source/drain regions.
2Reliability
If a metal gate is employed to reduce resistance, then the operating speed is improved, but the metal gate may be dissolved in wet-etching solution during the salicide process
Solution Approach 1:
The silicide layer is formed on the source/drain regions before metal gate deposition and before the wet-etching step of the salicide process. This preliminary formation creates a protective silicide layer that prevents the wet-etching solution from attacking and dissolving the metal gate electrode, thereby protecting the metal gate from damage while still allowing the metal gate to provide low resistance for high operating speed.
Solution Approach 2:
The silicide layer acts as an intermediary protective layer between the wet-etching solution and the metal gate electrode. This intermediate layer prevents direct contact between the harmful etching solution and the metal gate, thereby protecting the gate from dissolution while allowing the metal gate to function with low resistance.
3Productivity
If the gate line width is reduced compared to gate height, then high integration is achieved, but it becomes difficult to deposit metal material uniformly during the salicide process
Solution Approach 1:
The silicide layer is formed on the source/drain regions before the metal gate deposition step. This preliminary formation establishes a defined surface topology with the silicide layer covering the source/drain regions, which facilitates subsequent uniform metal deposition during the salicide process even when the gate line width is reduced for high integration.
4Productivity
If highly integrated semiconductor devices are manufactured, then the device density is improved, but the manufacturing margin is reduced and misalignment probability increases
Solution Approach 1:
The silicide layer is formed on the source/drain regions before subsequent alignment-critical steps including metal gate deposition and contact hole formation. This preliminary formation provides a stable reference surface and protective layer that reduces the impact of misalignment, thereby enabling high device density while mitigating the increased misalignment probability associated with reduced manufacturing margins.
Solution Approach 2:
The silicide layer acts as an intermediary protective and reference layer that reduces the sensitivity of subsequent processes to misalignment. This intermediate layer provides a stable surface for subsequent deposition and patterning steps, thereby reducing the impact of misalignment that becomes more probable in highly integrated devices with reduced manufacturing margins.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance, prevents damage to the metal gate, and enhances the efficiency of subsequent processes by maintaining a low aspect ratio and uniform deposition, thereby improving the manufacturing margin and operating speed of semiconductor devices.
Implementation Method 1
forming a silicide layer on the exposed source/drain region
Data Source
AI summary
Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.