Semiconductor Source/Drain Silicide Formation via Stacked Insulating Films
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Solution Overview
Problem
As semiconductor devices become highly integrated, the miniaturization of field effect transistors leads to increased gate and source/drain resistance, hindering high-speed operation, and existing salicide technologies face challenges in reliably forming low-resistance metal silicide layers.
Innovation Solution
A method of manufacturing a semiconductor device involving ion implantation for source/drain region formation, followed by a series of heat treatments and insulating film formations to create a metal silicide layer on the source/drain regions, using a stacked film of insulating films ZM1 and ZM2 to prevent impurity escape and reduce crystal defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If field effect transistors are miniaturized based on scaling rule, then integration density is improved, but gate and source/drain resistance increases
Solution Approach 1:
The patent applies segmentation by dividing the source/drain structure into multiple functional regions: lightly-doped drain (LDD) regions adjacent to the gate, and heavily-doped source/drain regions at the contacts. This segmentation allows each region to be optimized independently - LDD regions reduce hot carrier effects while heavily-doped regions provide low resistance paths, thus maintaining electrical performance despite miniaturization.
Solution Approach 2:
The patent implements local quality by applying different doping concentrations to different spatial locations within the source/drain structure. Specifically, the LDD regions receive lower doping concentrations (1E18 to 1E20 atoms/cm³) while the contact regions receive higher doping concentrations (1E19 to 1E21 atoms/cm³). This localized variation in material properties optimizes both device reliability and electrical characteristics.
2Reliability
If salicide technology is used to form metal silicide layer, then source/drain resistance is reduced, but manufacturing precision and reliability are compromised
Solution Approach 1:
The patent applies preliminary action by forming the insulating film (silicide block film) on the semiconductor substrate before performing ion implantation to create the source/drain regions. This preliminary insulating film acts as a barrier during subsequent processing steps, preventing unwanted silicide formation in regions where it would compromise manufacturing precision, while still allowing low-resistance contacts where needed.
Solution Approach 2:
The patent introduces an insulating film as an intermediary layer between the semiconductor substrate and the metal layer during salicide formation. This intermediary film selectively prevents silicide formation in certain regions (such as channel areas) while allowing it in contact regions, thereby achieving both low resistance and high manufacturing precision through spatially selective silicide formation.
3Reliability
If heat treatment is performed after ion implantation, then impurity activation is improved, but impurity escape and crystal defects increase
Solution Approach 1:
The patent applies preliminary action by forming the insulating film (silicide block film) on the semiconductor substrate before performing ion implantation to create the source/drain regions. This preliminary insulating film acts as a barrier during subsequent processing steps, preventing unwanted silicide formation in regions where it would compromise manufacturing precision, while still allowing low-resistance contacts where needed.
Solution Approach 2:
The patent introduces an insulating film as an intermediary layer between the semiconductor substrate and the metal layer during salicide formation. This intermediary film selectively prevents silicide formation in certain regions (such as channel areas) while allowing it in contact regions, thereby achieving both low resistance and high manufacturing precision through spatially selective silicide formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of semiconductor devices by maintaining consistent impurity concentration, preventing impurity escape, and reducing crystal defects, thereby improving the electrical characteristics and operational speed.
Implementation Method 1
a step of forming a source/drain region for MISFET in a semiconductor substrate by ion implantation
Implementation Method 2
a step of carrying out second heat treatment to react the metal film with the source/drain region and thereby form a metal silicide layer on the source/drain region
Data Source
AI summary
To provide a semiconductor device having improved reliability. After formation of an n+ type semiconductor region for source/drain, a first insulating film is formed on a semiconductor substrate so as to cover a gate electrode and a sidewall spacer. After heat treatment, a second insulating film is formed on the first insulating film and a resist pattern is formed on the second insulating film. Then, these insulating films are etched with the resist pattern as an etching mask. The resist pattern is removed, followed by wet washing treatment. A metal silicide layer is then formed by the salicide process.