Semiconductor Device Silicon Oxide Bitline Spacers Parasitic Capacitance
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Solution Overview
Problem
Conventional trench gate type semiconductor devices face issues with high parasitic capacitance due to the use of silicon nitride films as dielectric layers between bitlines and conductive layers, leading to reduced operational speed and increased contact resistance.
Innovation Solution
The semiconductor device employs silicon oxide film as bitline spacers instead of silicon nitride, reducing parasitic capacitance and allowing for faster operation by insulating diffusion layers from the bitline, and incorporates a snaking bitline structure to minimize the need for memory element contact plugs and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon nitride films are used as dielectric layers between bitlines and conductive layers, then good insulation is achieved, but parasitic capacitance increases leading to reduced operational speed
Solution Approach 1:
The patent changes the dielectric material parameter from silicon nitride to silicon oxide, which has different electrical properties. Silicon oxide provides adequate insulation while reducing parasitic capacitance, thereby improving operational speed without sacrificing reliability
2Ease of manufacture
If conventional bitline structures are used, then simple fabrication is achieved, but high contact resistance occurs due to the need for memory element contact plugs
Solution Approach 1:
The patent introduces a snaking bitline structure that extends in a meandering pattern, increasing the bitline length and allowing it to closely approach memory element contact plugs without requiring additional vertical stacking or complex 3D arrangements. This dimensional approach reduces contact resistance while maintaining fabrication simplicity
3Quantity of substance
If additional contact plugs are added to increase capacitance, then memory capacity improves, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent employs a snaking (curved/meandering) bitline structure that increases the effective bitline length and allows closer approach to memory element contact plugs. This curved path arrangement increases capacitance through enhanced electric field coupling without requiring additional contact plugs or complex 3D structures, thereby improving memory capacity while maintaining fabrication simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in reduced parasitic capacitance, faster operation, and higher production yield by using silicon oxide spacers and a snaking bitline structure, which also allows for a close-packed arrangement of capacitors, increasing capacitance without the need for additional contact plugs.
Implementation Method 1
silicon oxide film as bitline spacers instead of silicon nitride, reducing parasitic capacitance and allowing for faster operation by insulating diffusion layers from the bitline
Data Source
AI summary
There is provided an apparatus includes a substrate having a main surface, a wordline buried in the substrate and a bitline buried in a shallower area than the wordline in the substrate.