Semiconductor Simulation Modeling Flat and Corner Transistors
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Solution Overview
Problem
Current semiconductor device simulation methods fail to accurately reflect undesired electrical characteristics, leading to significant differences between measured and simulated device performance, particularly in the hump phenomenon of metal-oxide semiconductor (MOS) transistors.
Innovation Solution
A method and apparatus for simulating semiconductor devices by modeling flat and corner transistors within a simulation device, adjusting device parameters to accurately calculate and display electrical output signals, and determining manufacturing processes to alleviate the hump phenomenon, involving input interfaces, processors, and memory for precise parameter input and calculation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional simulation device is used, then the simulation process is simple, but the simulation accuracy of electrical characteristics is poor
Solution Approach 1:
The semiconductor device is segmented into multiple transistor models including a first transistor model for a flat transistor and a second transistor model for a corner transistor. This segmentation allows the simulation device to accurately represent different physical regions (flat and corner areas) of the semiconductor device, thereby improving simulation accuracy without requiring a single overly complex model.
Solution Approach 2:
Different transistor models are assigned to different local regions of the semiconductor device. The first transistor model specifically represents the flat transistor in the center portion, while the second transistor model represents the corner transistor at the edge portion. This local quality approach ensures that each region is simulated with appropriate characteristics, improving overall simulation accuracy.
2Measurement precision
If detailed transistor models are used, then the electrical characteristics are accurately simulated, but the calculation time increases
Solution Approach 1:
The semiconductor device is segmented into multiple transistor models including a first transistor model for a flat transistor and a second transistor model for a corner transistor. This segmentation allows the simulation device to accurately represent different physical regions (flat and corner areas) of the semiconductor device, thereby improving simulation accuracy without requiring a single overly complex model.
Solution Approach 2:
Different transistor models are assigned to different local regions of the semiconductor device. The first transistor model specifically represents the flat transistor in the center portion, while the second transistor model represents the corner transistor at the edge portion. This local quality approach ensures that each region is simulated with appropriate characteristics, improving overall simulation accuracy.
Data Source
AI summary
Provided are an apparatus and a method for simulating a semiconductor device. The method includes: modeling, through an input interface of a simulation device, a flat transistor as a first transistor; modeling, through the input interface, a first corner transistor as a second transistor; and calculating, by a processor of the simulation device, an output electrical signal in response to an input electrical signal applied to the first transistor and the second transistor to simulate at least one electrical characteristic of the semiconductor device. The flat transistor is formed by an active region defined by an isolation region on a semiconductor substrate, a gate electrode extending from the isolation region across the active region, and an impurity region in a portion of the active region. The first corner transistor is formed by an overlapping of the gate electrode and a first edge portion of the active region.