Semiconductor Simulation via Graph Neural Network Initial Solutions
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Solution Overview
Problem
Conventional semiconductor device simulators face significant execution time challenges due to the need for iterative calculations with nonlinear equations, and existing neural network solutions struggle with sampling electrostatic potential in complex three-dimensional shapes and adapting to structure changes.
Innovation Solution
A semiconductor device simulation system utilizing a region graph and graph artificial neural network to automatically analyze semiconductor device structures, generating an initial solution without user intervention, and enabling simulation of deformed structures without additional training.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If iterative calculation is used to solve nonlinear equations in semiconductor device simulation, then complete solution accuracy is improved, but execution time increases significantly
Solution Approach 1:
The system performs preliminary action by using the graph neural network to predict an initial potential distribution before the iterative calculation begins. This predicted initial value is prepared in advance based on the device structure, allowing the iterative solver to start from a much closer point to the final solution, thereby reducing the number of iterations required while maintaining complete solution accuracy.
2Productivity
If conventional neural network methods are used to predict initial values, then simulation speed is improved, but the method fails to handle complex three-dimensional shapes and structure changes effectively
Solution Approach 1:
The invention transitions from conventional grid-based or point-based neural network approaches to a graph-based representation where device structures are modeled as graphs with nodes and edges. This dimensional change in representation allows the neural network to naturally handle complex three-dimensional shapes and topological variations, as graph structures can represent arbitrary connectivity and spatial relationships without being constrained by regular grids.
Solution Approach 2:
The system changes the fundamental parameters of the neural network approach by using graph neural networks instead of conventional neural networks. This parameter change in the network architecture enables the system to adapt to various device structures and configurations, maintaining simulation speed while significantly improving versatility and adaptability to structure changes.
3Measurement precision
If additional training is performed for deformed structures, then simulation accuracy for specific structures is improved, but training time and computational overhead increase
Solution Approach 1:
The graph neural network is designed with universal applicability to handle various semiconductor device structures and configurations. By training on diverse graph representations of device structures, the network learns general patterns and relationships that can be applied to different device types and deformations without requiring additional structure-specific training, thereby maintaining simulation accuracy while avoiding redundant training overhead.
Data Source
AI summary
Provided is a semiconductor device simulation system using region graph. The semiconductor device simulation system comprises: a region graph generation module for generating a region graph using a device structure file of a semiconductor device to be simulated; a device determination module for determining a type of semiconductor device for the region graph using a trained graph artificial neural network; an initial solution generating module for generating an initial solution for a device structure corresponding to the type of semiconductor device; and a semiconductor device simulator for performing semiconductor device simulation using the initial solution. The semiconductor device simulation system accelerates the speed of performing semiconductor device simulation by providing an approximate initial solution to the device structure to a semiconductor device simulator.