Semiconductor Simulation Initial Guess via Pseudo 1D Continuity Integration
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Solution Overview
Problem
Conventional semiconductor device simulators face inefficiencies in generating an initial guess for nonlinear equations, leading to prolonged simulation times due to the need for iterative calculations, especially when simulating 3D semiconductor devices, as they lack accurate physical quantity information across all positions.
Innovation Solution
A method employing a pseudo 1D model to solve the electron or hole continuity equation along the channel direction, generating integrated electron charge density and quasi-Fermi potential for 2D cross sections, which are then used to calculate physical quantities at each position, providing these as initial guesses for the simulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional semiconductor device simulators use iterative calculations to solve nonlinear equations, then accurate solutions can be obtained, but simulation time increases significantly
Solution Approach 1:
The patent applies preliminary action by using a compact charge model to pre-calculate and provide an initial guess for the physical quantities (electron/hole concentration and electrostatic potential) at all positions in the semiconductor device before the main simulation starts. This initial guess is generated by integrating the continuity equation along the channel direction and applying boundary conditions, thereby avoiding the need to start from equilibrium and ramp voltage step-by-step during the actual simulation.
2Reliability
If simulators ramp voltage step-by-step from initial settings to obtain solutions, then complete solutions can be obtained, but most execution time is spent on intermediate process calculations
Solution Approach 1:
The compact charge model performs preliminary calculation of physical quantities at all positions by integrating the continuity equation along the channel direction and applying boundary conditions, generating an initial guess that directly corresponds to the desired target voltage condition. This eliminates the need for time-consuming step-by-step voltage ramping and intermediate process calculations while ensuring complete and accurate solutions.
Solution Approach 2:
The patent uses a simplified compact charge model that copies the essential physics of the semiconductor device in an integrated form. This model reproduces the key characteristics (current-voltage relationships, charge distribution) without the full complexity of 3D simulations, allowing rapid generation of initial guesses that capture the necessary physical behavior.
3Productivity
If compact charge models are used to calculate terminal currents, then computational efficiency improves, but physical quantity information at each position is lost
Solution Approach 1:
The patent segments the semiconductor device into discrete positions along the channel direction and calculates physical quantities at each position independently using the continuity equation integration. This segmentation allows the compact charge model to maintain spatial distribution information while preserving computational efficiency, as each position can be processed separately without requiring full 3D simulation.
Solution Approach 2:
The patent transitions from terminal-level calculations (0D) to position-level calculations (1D along the channel). By integrating the continuity equation along the channel direction and solving for physical quantities at each position, the model adds the spatial dimension while maintaining the efficiency of compact models. This dimensional transition restores lost spatial information without sacrificing computational performance.
Data Source
AI summary
Provided is a method for generating an initial guess for simulating a semiconductor device. The method includes; (a) setting 1D direction for a 3D semiconductor device to be simulated and 2D cross sections perpendicular to the 1D direction; (b) setting a charge intensity-gate voltage model for the 2D cross sections; (c) numerically solving an electron or hole continuity equation along the 1D direction to detect integrated electron charge density and quasi-Fermi potential for the 2D cross sections; and (d) calculating a physical quantity for each position of the 2D cross sections by applying the integrated electron charge density and the quasi-Fermi potential for the 2D cross sections to the charge density-gate voltage model, and providing the calculated physical quantity as the initial guess for the semiconductor device simulation. Therefore, the initial solution according to the present invention can accelerate the speed of the semiconductor device simulation.