Semiconductor Structure Fabrication Using Single Photomask Integration
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Solution Overview
Problem
The existing process for fabricating semiconductor structures with both memory units and resistors is complex and costly, requiring multiple photomasks and separate process steps, which increases production costs and reduces competitiveness.
Innovation Solution
A method is developed to integrate the formation of semiconductor structures with memory units and resistors using a single photomask, where a stacked structure with a gate oxide layer, floating gate, and inter-gate dielectric layer forms a charge storage structure, and a salicide block layer is used simultaneously with the resistor, allowing for shared doped regions and reduced process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate processes are used for fabricating memory units and resistors, then each component can be optimized independently, but the process complexity and cost increase significantly
Solution Approach 1:
The patent combines the fabrication processes for memory units and resistors into a single integrated process. The resistor is formed within the memory cell structure during the same process steps that create the memory unit, eliminating the need for separate fabrication processes. This merging approach reduces process complexity while maintaining the ability to optimize both components through unified process control.
Solution Approach 2:
The patent creates a multi-functional structure where the same fabrication process serves dual purposes: forming both the memory unit and the resistor. The process uses common materials and steps (such as the conductive material layer and doping processes) to create both functional elements, making the process universal rather than specialized for separate components.
2Manufacturing precision
If multiple photomasks are used for separate fabrication processes, then precise patterning can be achieved for each component, but the manufacturing cost and time increase
Solution Approach 1:
The patent merges the patterning steps for memory units and resistors into a single photomask process. The photomask is designed with patterns that define both the memory unit structure and the resistor location simultaneously. This single-step patterning achieves the necessary precision for both components while eliminating the costs and time associated with multiple photomask fabrication and alignment steps.
3Ease of manufacture
If integrated fabrication is implemented, then process cost and complexity are reduced, but achieving both memory unit and resistor electrical requirements becomes more difficult
Solution Approach 1:
The patent applies local quality by using the same fabrication process with different local parameters to create components with different electrical characteristics. The memory unit and resistor are formed using identical process steps, but local variations in material composition, layer thickness, and doping concentrations are controlled to achieve the distinct electrical requirements of each component. This allows integrated fabrication while maintaining electrical performance through localized process optimization.
Data Source
AI summary
A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.