Semiconductor Package Insulating Layer Layout for Crack-Free Singulation
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Solution Overview
Problem
The increasing integration density and precision of semiconductor devices demand higher reliability and lower failure rates, which existing manufacturing processes have not adequately addressed, particularly in the singulation of wafers into semiconductor chips.
Innovation Solution
A semiconductor device and package design featuring a semiconductor substrate with an insulating layer and passivation layer configuration, including a central portion with parallel side surfaces and corner protrusions, which are spaced apart to enhance structural integrity and reduce stress during chip separation, thereby minimizing failure rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the insulating layer and passivation layer are removed in scribe lanes to enable chip separation, then chip singulation is achieved, but cracking and particle formation occur reducing reliability
Solution Approach 1:
The insulating layer is divided into a first insulating layer and a second insulating layer separated by a scribe lane. The first insulating layer is removed in the scribe lane region while the second insulating layer remains, creating a segmented structure that enables chip separation while maintaining structural integrity and preventing cracking during the singulation process.
Solution Approach 2:
The patent performs preliminary removal of the first insulating layer in the scribe lane region before chip separation. This preliminary action creates a pre-defined separation path that guides the singulation process and prevents uncontrolled cracking, thereby maintaining reliability while enabling productivity.
2Productivity
If stress is applied to separate chips from the wafer, then chip separation is achieved, but particles are generated increasing failure rate
Solution Approach 1:
The insulating layer structure is segmented into two distinct layers with different removal patterns. The first insulating layer is selectively removed in scribe lanes to create clean separation paths, while the second insulating layer remains to provide structural support during stress application, thereby enabling chip separation without generating particles.
Solution Approach 2:
The second insulating layer acts as an intermediary structure that remains during the separation process. It serves as a mediator between the applied stress and the chip structure, allowing controlled separation while preventing direct contact and particle generation between chips and the wafer.
3Productivity
If complete removal of insulating layers is performed for chip separation, then singulation is achieved, but structural integrity is compromised leading to cracking
Solution Approach 1:
The insulating layer is segmented into two functional layers: the first layer is completely removed in scribe lanes to enable separation, while the second layer is selectively retained to maintain structural integrity. This segmentation allows chip singulation to proceed without compromising the overall structural strength of the wafer.
Solution Approach 2:
Different regions of the insulating layer structure are treated with different quality levels. In scribe lane regions, the first insulating layer is completely removed for separation. In chip regions, the second insulating layer is preserved to maintain structural integrity, creating local quality variations that satisfy both singulation and strength requirements.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a semiconductor device on an active surface thereof. The semiconductor substrate has a quadrangular plane. An insulating layer is on the active surface of the semiconductor substrate. A passivation layer is on the insulating layer. The insulating layer includes an insulating layer central portion having a side surface extending in parallel with a side surface of the semiconductor substrate. The side surface of the insulating layer central portion is spaced apart from the side surface of the semiconductor substrate by a first size. An insulating layer corner portion is at each corner of the insulating layer central portion and protrudes from the side surface of the insulating layer central portion in a horizontal direction. The passivation layer covers the insulating layer central portion.