Semiconductor Chip Singulation via Metal-Filled Dicing Trenches
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for singulating semiconductor wafers into chips are inefficient, leading to low yields due to constraints on the singulation process, and often result in high material waste and complex processing steps.
Innovation Solution
A method involving a composite structure with a semiconductor layer sequence and a filling layer, where dicing trenches are formed along a singulation pattern, and a metal layer is applied and subsequently removed to facilitate efficient and gentle singulation, allowing for high surface utilization and low scrap rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional singulation methods are used to dice semiconductor wafers into chips, then the singulation process can be performed, but the yield is limited due to constraints on the singulation process resulting in low efficiency and high material waste
Solution Approach 1:
The patent applies preliminary action by forming dicing trenches and applying a metal layer before the actual singulation process. The metal layer is deposited in advance to fill the trenches, providing mechanical support and enabling more precise cutting paths. This preliminary preparation allows for narrower dicing streets and reduces material waste during singulation.
Solution Approach 2:
The patent introduces a metal layer as an intermediary substance that fills the dicing trenches. This metal layer acts as a mediator between the semiconductor structure and the singulation process, providing mechanical stability and enabling precise cutting. The intermediary metal layer reduces direct contact between the cutting tool and the semiconductor material, minimizing damage and material loss.
2Ease of manufacture
If conventional singulation methods are used, then the process can be completed, but the constraints on the singulation process result in complex processing steps and low yield
Solution Approach 1:
The dicing trenches are formed and metal layer is applied in advance before singulation. This preliminary action simplifies the actual cutting process by providing pre-prepared guides and support structures, making the singulation step easier to execute with higher precision and yield.
Solution Approach 2:
The patent changes the physical and chemical parameters of the dicing trenches by filling them with metal material. This parameter change transforms the trenches from empty spaces into structurally sound guides that facilitate easier and more accurate singulation, improving both manufacturing ease and yield.
3Area of stationary object
If wide dicing streets are used for singulation, then the singulation process is simpler, but the surface utilization is reduced and more material is wasted
Solution Approach 1:
The metal layer serves as an intermediary that enables narrow dicing streets to be used effectively. By filling the trenches with metal, the structure gains sufficient mechanical strength to support tight cutting paths, allowing narrow streets that maximize surface utilization while maintaining manufacturing feasibility.
Solution Approach 2:
The patent creates a composite structure by combining the semiconductor material with the metal filling in the dicing trenches. This composite approach allows the use of narrower dicing streets because the metal provides additional structural support, enabling tighter spacing without compromising the ease of the singulation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables efficient and gentle singulation of semiconductor chips with narrow dicing streets, high yield, and reduced material loading, simplifying further processing and ensuring mechanical stabilization of the chips.
Implementation Method 1
The semiconductor layer sequence is for example deposited epitaxially, for instance by means of sputtering, MOVPE, MOCVD or MBE
Implementation Method 2
a metal layer adjoining the filling layer is applied in the dicing trenches
Data Source
AI summary
Disclosed is a method for producing a plurality of semiconductor chips (10). A composite (1), which comprises a carrier (4) and a semiconductor layer sequence (2, 3), is provided. Separating trenches (17) are formed in the semiconductor layer sequence (2, 3) along an isolation pattern (16). A filling layer (11) limiting the semiconductor layer sequence (2, 3) toward the separating trenches (17) is applied to a side of the semiconductor layer sequence (2, 3) facing away from the carrier (4). Furthermore, a metal layer (10) adjacent to the filling layer (11) is applied in the separating trenches (17). The semiconductor chips (20) are isolated by removing the metal layer (10) adjacent to the filling layer (11) in the separating trenches (17). Each isolated semiconductor chip (20) has one part of the semiconductor layer sequence (2, 3), and of the filling layer (11). Also disclosed is a semiconductor chip (10).