Semiconductor Module Sintering Layout for Uniform Chip Bonding

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Solution Overview

Problem

Conventional sintering methods for bonding semiconductor chips to insulating circuit boards result in uneven electrical and thermal characteristics due to incomplete pressurization of sintering materials, leading to mechanical weaknesses and potential cracking, which degrades the performance and reliability of semiconductor modules.

Innovation Solution

A method involving the arrangement of sintering materials on an insulating wiring board, with semiconductor chips placed on top, and a structure above the protruding sintering material edges, allowing for uniform pressurization and heating through both the chips and the structure to ensure consistent bonding density across the sintered metal layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If sintering material is formed larger than semiconductor chip to increase bonding area, then bonding area is improved, but pressurization uniformity deteriorates

Engineering Contradiction:
Improvebonding areaVSAvoidpressurization uniformity
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The sintering material is divided into two distinct regions: a first sintering material positioned directly beneath the semiconductor chip for primary bonding, and a second sintering material extending beyond the chip periphery to increase overall bonding area. This segmentation allows each region to be optimized independently for its specific function.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the sintering material structure are given different properties and positions. The first sintering material is located at the center under the chip for direct pressurization, while the second sintering material is positioned at the periphery to extend bonding area. This local differentiation resolves the contradiction between area and pressurization uniformity.

Inventive Principle:
Principle #3Local quality

2Strength

If sintering material is pressurized through semiconductor chip only, then bonding strength at chip location is improved, but sintering material density at protruding portions deteriorates

Engineering Contradiction:
Improvebonding strengthVSAvoidsintering material density
Core Design Contradiction:
StrengthVSManufacturing precision

Solution Approach 1:

The sintering material is segmented into a first portion under the chip and a second portion extending beyond the chip periphery. This allows the first portion to receive direct pressurization for strong bonding, while the second portion is separately ensured to achieve adequate density through the extended configuration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The sintering material structure extends in the planar dimension beyond the chip boundaries, creating a multi-regional structure. This dimensional extension allows different areas to serve different purposes: central area for strength-critical bonding, peripheral area for density-critical sintering.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Area of stationary object

If sintering material is formed one size larger than semiconductor chip, then contact area is improved, but mechanical characteristics at protruding portions deteriorate

Engineering Contradiction:
Improvecontact areaVSAvoidmechanical characteristics
Core Design Contradiction:
Area of stationary objectVSStrength

Solution Approach 1:

The sintering material structure implements local quality differentiation where the first sintering material under the chip provides optimized mechanical characteristics through direct pressurization, while the second sintering material at the periphery provides extended contact area. Each local region is optimized for its specific requirement.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The sintering material is segmented into functional zones: a central first sintering material zone for mechanical strength and a peripheral second sintering material zone for contact area extension. This segmentation allows the overall structure to achieve both extended contact area and adequate mechanical characteristics.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach prevents performance and reliability degradation by ensuring uniform mechanical, electrical, and thermal characteristics across the sintered metal layers, reducing the likelihood of cracking and enhancing the overall integrity of the semiconductor module.

Implementation Method 1

heat is applied while pressing and pressurizing upper surfaces of the semiconductor chips to cause a sintering reaction in the sintering material

Methodology Applied
Scientific EffectSintering: Sintering

Data Source

PatentUS20240055391A1Method for manufacturing semiconductor module
Publication Date: 2024.02.15 FUJI ELECTRIC CO LTD
  • US20240055391A1 patent drawing
  • US20240055391A1 patent drawing
  • US20240055391A1 patent drawing

AI summary

A method for manufacturing a semiconductor module can prevent performance and reliability degradation of a semiconductor module. The method for manufacturing a semiconductor module includes: arranging an insulating wiring board on a low die; arranging a sintering material at plural locations on the insulating wiring board and arranging a semiconductor chip on each of the plural sintering materials; arranging a structure above protruding portions of the sintering materials protruding from a periphery of each of the plural semiconductor chips; and sintering by pressurizing and heating the plural sintering materials by an upper die through the structure at the protruding portions and through the semiconductor chips at contacting portions in contact with lower surfaces of the semiconductor chips.