Semiconductor Structure With SiO2 Diffusion Barrier for Leakage Control
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Solution Overview
Problem
Group III nitride devices on silicon substrates face issues of parasitic capacitance and leakage current due to element diffusion, which compromises device reliability.
Innovation Solution
A manufacturing method involving a Si-supporting substrate with a SiO2 protection layer, a thin SiO2 intermediate layer, and a Si growth substrate with n-type doping, along with trenches in the intermediate layer to block element diffusion and compensate for diffused elements, thereby reducing parasitic capacitance and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a group III nitride device layer is formed on a silicon substrate, then the device can be manufactured with excellent electrical characteristics, but element diffusion occurs from the device layer into the silicon substrate forming p-type regions that cause parasitic capacitance and leakage current
Solution Approach 1:
An SiO2 intermediate layer is introduced between the silicon substrate and the group III nitride device layer. This intermediate layer acts as a diffusion barrier that blocks element diffusion from the device layer into the silicon substrate, preventing the formation of p-type regions that cause parasitic capacitance and leakage current, while still allowing the device to function properly
Solution Approach 2:
The original direct contact interface between the silicon substrate and device layer is segmented by inserting the SiO2 intermediate layer. This segmentation creates a barrier that separates the silicon substrate from the group III nitride elements, preventing harmful diffusion while maintaining device functionality
2Ease of manufacture
If the SiO2 protection layer is completely removed to form a direct interface, then manufacturing process is simplified, but element diffusion increases causing parasitic capacitance and leakage current
Solution Approach 1:
The SiO2 protection layer is thinned to a controlled thickness (less than 1 nm, less than or equal to a single atomic layer) before device layer formation. This preliminary thinning action maintains the diffusion barrier function of SiO2 while reducing the layer thickness to minimize impact on device performance and manufacturing complexity
3Object-generated harmful factors
If a thick SiO2 intermediate layer is used to block element diffusion, then parasitic capacitance and leakage current are reduced, but mechanical strength and interface quality may be compromised
Solution Approach 1:
The thickness of the SiO2 intermediate layer is precisely controlled to be less than 1 nm, and in some embodiments less than or equal to a single atomic layer. This parameter optimization maintains the diffusion barrier function while preserving mechanical strength and interface quality, as excessive thickness would create stress and potential delamination issues
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively inhibits element diffusion, enhances mechanical strength, and improves device reliability by minimizing parasitic capacitance and leakage current.
Implementation Method 1
The SiO2 intermediate layer provided in the present disclosure may effectively reduce the diffusion of an element such as Ga/Al in a group III-V material device layer to the substrate
Implementation Method 2
An n-type doped Si growth substrate provided in the present disclosure may further perform compensation doping on a diffused element such as Ga/Al, to further avoid parasitic capacitance and leakage current
Data Source
AI summary
A manufacturing method for a semiconductor structure includes: providing a Si-supporting substrate having a SiO2 protection layer on a surface of the Si-supporting substrate; thinning the SiO2 protection layer to form a SiO2 intermediate layer; disposing a Si growth substrate on a side, away from the Si-supporting substrate, of the SiO2 intermediate layer; and disposing a device layer on a side, away from the Si-supporting substrate, of the Si growth substrate. The technical solutions of the present disclosure may reduce a possibility of generating parasitic capacitance and leakage current, and greatly improve the reliability of a device.