Self-Test Circuit for Semiconductor Timing Skew Margin
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Solution Overview
Problem
High-speed semiconductor integrated circuits face challenges in accurately checking the setup and hold times of input signals due to signal delay variations, requiring precise timing adjustments over a wide range, which is difficult with current external testers and increases manufacturing costs.
Innovation Solution
A semiconductor integrated circuit with a built-in checking circuit that includes flip-flop circuits, timing control circuits, and phase-locked loop circuits to self-check the timing relationship between input signals and adjust the timing of these signals over a wide range, reducing the need for external devices and simplifying the configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external LSI testers are used to check timing relationships with high resolution (100 psec or lower), then measurement precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements a built-in self-test circuit within the semiconductor integrated circuit that generates test signals and performs timing measurements internally. The test signal generation circuit creates clock and data signals, while the measurement circuit measures timing relationships without requiring external test equipment, thereby achieving high-precision measurement while reducing device complexity and manufacturing cost.
Solution Approach 2:
The patent introduces an intermediate measurement circuit that acts as a mediator between the test signals and the timing measurement function. This measurement circuit includes delay circuits and coincidence detection circuits that facilitate precise timing measurement through intermediate signal processing, enabling high-precision measurement without complex external test systems.
2Measurement precision
If external high-speed testers are used for AC testing, then measurement precision is improved, but ease of manufacture deteriorates due to expensive equipment and difficult stable production line testing
Solution Approach 1:
The built-in self-test circuit performs high-speed signal AC testing autonomously within the semiconductor integrated circuit. The test signal generation circuit produces high-speed clock and data signals, and the measurement circuit accurately measures timing relationships, eliminating the need for expensive external high-speed testers and simplifying production line testing.
Solution Approach 2:
The patent extracts the timing measurement function from external test equipment and incorporates it directly into the semiconductor integrated circuit. By taking out the measurement function and integrating it with the test signal generation circuit, the system achieves high-speed signal testing capability without requiring complex external test equipment, thereby improving ease of manufacture.
3Adaptability or versatility
If timing adjustment is performed over a wide range to account for manufacturing variations, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements a dynamic timing adjustment mechanism where the measurement circuit can vary timing parameters over a wide range to accommodate manufacturing variations. The delay circuits and coincidence detection circuits enable flexible timing adjustment, allowing the circuit to adapt to different timing requirements while maintaining a relatively simple structure through dynamic parameter changes rather than static complex circuitry.
Data Source
AI summary
A semiconductor integrated circuit that self-tests the skew margin of the clock and data signals in an LVDS. A clock signal CKB1 is held in flip-flop circuit 105 synchronously with checking clock signal A1. Checking pattern signal PAT_A is held in flip-flop circuit 104 synchronously with checking clock signal A2. When the skew margin of clock signal CKA_IN and data signal DA_IN are checked, the checking signal TCKA of flip-flop circuit 105 is input instead of clock signal CKA_IN, and the checking signal TDA of flip-flop circuit 104 is input instead of clock signal DA_IN. The timing relationship between clock signal CKB7 and checking timing signal A1 and the timing relationship between clock signal CKB7 and checking timing signal A2 are controlled independently by timing control circuit 109.