Semiconductor Slit Alignment via Impedance Detection
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Solution Overview
Problem
The existing semiconductor devices face reliability issues due to potential misalignment of machining positions in the through-holes and slits, which can lead to improper connection with the host, affecting data transfer and power supply efficiency.
Innovation Solution
The semiconductor device incorporates test patterns and terminals around the through-holes to detect machining position offsets by measuring impedance, ensuring accurate alignment and preventing misalignment of the slit and through-hole positions during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional manufacturing processes are used for through-holes and slits, then manufacturing simplicity is maintained, but machining position misalignment occurs leading to reliability issues
Solution Approach 1:
The patent applies preliminary action by forming test patterns and test terminals before the final product assembly. These test structures are created during the manufacturing process to enable subsequent measurement and detection of machining position accuracy. The test patterns include conductive paths and terminals that are prepared in advance to facilitate impedance measurements for detecting misalignment between through-holes and slits, thereby ensuring connection reliability before the device is completed.
2Manufacturing precision
If machining positions are not monitored, then manufacturing process is simple, but misalignment occurs affecting data transfer and power supply efficiency
Solution Approach 1:
The patent implements feedback by creating a closed-loop measurement system using test patterns and test terminals. After machining the through-holes and slits, the impedance between test terminals is measured to detect any misalignment. This feedback mechanism allows the manufacturing process to monitor and evaluate machining position accuracy, enabling correction or rejection of defective products. The test patterns serve as reference structures that provide measurable feedback on the alignment quality of the connector features.
3Reliability
If test patterns and terminals are added to detect misalignment, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent uses test patterns and test terminals as intermediary elements that facilitate the detection of machining accuracy without being part of the final functional connector. These test structures act as mediators between the machining process and the quality assessment process. They enable indirect measurement of alignment accuracy through impedance measurements, allowing the system to evaluate connection reliability without requiring direct measurement of the through-hole and slit positions themselves.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of the connection between the semiconductor device and the host by accurately detecting and correcting machining position offsets, thereby improving data transfer and power supply efficiency.
Implementation Method 1
The substrate has test patterns and test terminals, and offset of a machining position of the through-hole with respect to a normal position can be determined based on a result of measurement of impedance between the test terminals
Data Source
AI summary
A semiconductor device includes a substrate, a nonvolatile semiconductor memory disposed on a surface of the substrate, and a controller disposed on a surface of the controller. The substrate has a slit on an edge on which interface connection terminals are formed, a ground pattern, first and second wiring patterns that are electrically connected to the ground pattern and extend in a direction in which the slit extends, and a through hole that is formed between the first and second wiring patterns and is large enough along a dimension between the first and second wiring patterns to span substantially all of the spacing between the first and second wiring patterns.