Semiconductor Package Small Gate Clip Assembly
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Solution Overview
Problem
Conventional semiconductor packaging methods using both wire bonding and metal clips for source and gate connections result in a complex process with low production yield and inability to support high currents and frequencies, and larger clips for gate connections lead to residue issues affecting device manufacturing.
Innovation Solution
A semiconductor package design featuring a small gate clip structure with two identical clip sets placed side by side, one inverted relative to the other, connected by tie bars forming an S-shaped or reverse S-shaped configuration, which simplifies the connection process and reduces residue, using metal clips for both source and gate connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If both wire bonding and metal clips are used for source and gate connections, then connection capability is improved, but process complexity increases and production yield decreases
Solution Approach 1:
The patent applies universality by using metal clips for both source and gate connections, making the same component serve multiple functions. This eliminates the need for separate wire bonding and clip bonding processes, simplifying the overall connection process while maintaining versatile connection capability for different electrodes.
Solution Approach 2:
The patent merges the connection methods for source and gate electrodes by using the same metal clip bonding technique for both. This combines previously separate processes (wire bonding for gate, clip bonding for source) into a unified approach, reducing process complexity and improving production yield.
2Adaptability or versatility
If larger clips are used for gate connection, then connection capability is improved, but residue issues increase affecting device manufacturing
Solution Approach 1:
The patent applies local quality by using different sized clips for different functions: smaller clips for gate connections and larger clips for source connections. Each clip size is optimized for its specific location and function, allowing the gate clip to be small enough to avoid residue issues while still providing adequate connection capability.
Solution Approach 2:
The patent inverts the conventional approach by using smaller clips for gate connections instead of larger clips. This reversal solves the residue problem by reducing clip size at the gate location while maintaining connection capability through the optimized clip design and bonding process.
3Device complexity
If wire bonding is used for gate connection, then process simplicity is improved, but current carrying capability and frequency support decrease
Solution Approach 1:
The patent replaces wire bonding (a mechanical joining process) with metal clip bonding for gate connections. This substitution maintains process simplicity while dramatically improving current carrying capability and frequency support, as metal clips provide better electrical contact and lower inductance compared to wire bonds.
4Power
If metal clips are used for both source and gate connections, then current carrying capability is improved, but clip size must be increased for gate connection causing residue problems
Solution Approach 1:
The patent applies local quality by optimizing clip size for each specific location: smaller clips for gate connections where residue must be minimized, and larger clips for source connections where current carrying capability is the primary concern. This localized optimization allows metal clips to be used for both connections without the residue problems that would result from using uniformly large clips.
Data Source
AI summary
A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted on the first and second semiconductor chips, wherein the first clip set is connected to the gate electrode of the first chip, the source electrode of the second chip, and their corresponding leads and the second clip set is connected to the gate electrode of the second chip, the source electrode of the first chip and their corresponding leads.