Semiconductor Device Snubber Circuit Surge Voltage Suppression
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Solution Overview
Problem
Parasitic inductance in semiconductor devices can cause surge voltages between the source and drain electrodes, leading to potential breakdown of insulated gate field-effect transistors, which existing snubber circuits with resistors and capacitors may not adequately address, resulting in reliability issues.
Innovation Solution
A semiconductor device design featuring a snubber circuit with a resistor and capacitor in a separate region of the substrate, where the second deep trenches are narrower and shallower than the first deep trenches, forming a snubber region that reduces surge voltages and enhances inductive load tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a snubber circuit with resistors and capacitors is provided to reduce surge voltages, then the reliability of the semiconductor device is improved, but the device complexity increases
Solution Approach 1:
The patent combines the snubber circuit components (resistors and capacitors) into a single integrated structure formed within the semiconductor substrate. The first and second deep trenches are merged to form a unified capacitor structure, while the insulating films and conductive layers are integrated into the substrate architecture. This merging reduces the overall device complexity by consolidating multiple components into a compact, unified design that maintains the surge voltage suppression function.
Solution Approach 2:
The patent implements a nested structure where the snubber circuit components are embedded within the semiconductor substrate layers. The capacitor is nested between the first and second deep trenches, with insulating films nested within the trenches. The resistor and capacitor are both nested within the substrate architecture, creating a multi-layered nested configuration that reduces spatial requirements and simplifies the overall device structure.
2Reliability
If the second deep trenches are made narrower than the first deep trenches, then the surge voltage reduction effectiveness is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by creating different trench widths at different locations within the semiconductor substrate. The second deep trenches are specifically made narrower than the first deep trenches to optimize the capacitor geometry and enhance surge voltage suppression in critical regions. This localized variation in trench dimensions allows the device to achieve superior performance in specific areas without requiring uniform high precision throughout the entire substrate, thereby balancing performance optimization with manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces surge voltages and prevents breakdown, increasing the reliability of insulated gate field-effect transistors by absorbing energy and controlling current flow, thereby enhancing the semiconductor device's operational stability.
Implementation Method 1
a snubber circuit formed in the second region other than the first region, and having a resistor and a capacitor
Implementation Method 2
The resistors and capacitors connected in series are electrically connected between the drain and source electrodes of the trench gate type power MOSFET
Data Source
AI summary
A semiconductor device with an insulated-gate field-effect transistor and its manufacturing method. The cell region EFR defined in the first region of one main surface side of semiconductor substrate (SUB), an insulated gate-type field-effect transistor (MFET) is formed, the gate pad region GPR defined in the first region, snubber circuit SNC is formed snubber region SNR is defined. Within the first and second regions, first and second deep trenches spaced apart from each other are formed, and at least one width of the plurality of second deep trenches formed in the second region is smaller than that of the first deep trench formed in the first region.