Semiconductor Package Alignment Solder Joints for Drift-Free Molding
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges such as warpage, chip drift, and surface coplanarity issues, which affect the precision and efficiency of chip placement and packaging, leading to increased equipment costs and reduced production speed.
Innovation Solution
A novel semiconductor packaging method utilizing alignment solder joints between semiconductor devices and a carrier board for precise self-alignment, combined with a clamping board for molding, eliminates the need for adhesive films and reduces thermal expansion mismatches, thereby preventing chip drift and rotation, and improving packaging efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If adhesive films are used for chip placement, then chip attachment is simplified, but thermal expansion mismatches cause chip drift and rotation reducing precision
Solution Approach 1:
The patent changes the bonding mechanism from adhesive-based to solder-based, utilizing the phase transition properties of solder material. By controlling the melting and solidification parameters of solder, the system achieves both ease of manufacture and high precision chip placement, eliminating thermal expansion mismatch issues that plague adhesive-based methods
Solution Approach 2:
The patent replaces the mechanical adhesive bonding system with a metallurgical solder bonding system. This substitution eliminates the thermal expansion mismatch problems inherent in adhesive films, as solder joints provide rigid mechanical and thermal coupling between the chip and substrate, preventing chip drift and rotation
2Manufacturing precision
If high precision mounting equipment is used for chip placement, then placement precision is improved, but equipment cost increases and production speed is limited
Solution Approach 1:
The patent implements self-alignment through solder joint formation, where the solder material automatically flows and bonds to align the chip with the substrate during the reflow process. This self-service alignment mechanism eliminates the need for expensive high-precision mounting equipment while maintaining placement precision and enabling faster batch processing
Solution Approach 2:
The patent extracts the alignment function from the mechanical mounting equipment and transfers it to the solder joint formation process. By taking out the precision requirement from the placement step and embedding it in the solder reflow process, the system achieves high precision without expensive equipment and enables higher production speeds
3Device complexity
If traditional packaging methods are used, then process simplicity is maintained, but warpage and surface flatness issues reduce package reliability
Solution Approach 1:
The patent employs a composite structure combining solder joints, molding compound, and substrate materials with different thermal and mechanical properties. This composite approach manages warpage by distributing thermal and mechanical stresses across multiple materials, improving package reliability while maintaining process simplicity through integrated manufacturing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances precision and speed of chip placement, reduces equipment costs, and improves packaging efficiency by using solder joints for alignment and a clamping board for molding, addressing warpage and coplanarity issues.
Implementation Method 1
forming a plurality of alignment solder joints by soldering the plurality of first alignment solder parts to respective ones of the plurality of second alignment solder parts
Data Source
AI summary
A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises providing at least one semiconductor device, a carrier board, and a clamping board. The at least one semiconductor device has a passive surface with first alignment solder parts formed thereon, and the carrier board has a plurality of corresponding second alignment solder parts formed thereon. The method further comprises forming alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts; and injecting a molding compound through one or more openings in one or both of the carrier board and the clamping board to form a molded package body encapsulating the at least one semiconductor device between the carrier board and the clamping board attached to the active surface of the at least one semiconductor device.