Semiconductor Package Solder Crack Control for Fan-Out Bonding
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Solution Overview
Problem
Conventional fan-in wafer-level packaging faces challenges with solder ball size and pitch issues, leading to bonding strength decreases and contact defects, and requires changes in wiring layouts as chip size changes, making it difficult to ensure reliability and increase manufacturing costs.
Innovation Solution
A fan-out wafer-level package method that includes forming a solder crack control part with a thickness twice that of the second insulating film on the redistribution layer, allowing for improved solder bonding characteristics by minimizing cracks and enabling standardized ball layouts, and incorporating a UBM pattern to enhance the bonding area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If solder balls are placed directly on metal pads in conventional fan-in packaging, then the bonding process is simple, but cracks occur on the chip pad under pressure, resulting in open circuits and reduced reliability
Solution Approach 1:
The patent introduces a solder crack control part as an intermediary structure between the solder ball and the metal pad. This control part has a greater thickness than the underlying insulating film, creating a stress-absorbing layer that prevents direct stress transmission to the pad, thereby eliminating cracks while maintaining bonding simplicity
Solution Approach 2:
The solder crack control part is formed in advance during the fabrication process, before solder ball attachment. Its greater thickness provides pre-established stress cushioning that prevents pad cracking when solder balls are subsequently attached and subjected to bonding pressure
2Volume of moving object
If chip size is reduced in fan-in packaging, then miniaturization is achieved, but solder ball size and pitch must be reduced, leading to decreased bonding strength and contact defects
Solution Approach 1:
The patent transitions from fan-in to fan-out packaging, moving I/O terminals and wiring from the chip interior to the exterior epoxy mold compound area. This dimensional relocation allows standard solder ball sizes and pitches to be used even with smaller chips, maintaining bonding strength while achieving miniaturization
3Volume of moving object
If fan-in packaging is used, then chip scale packaging is achieved, but wiring layout must be changed as chip size changes, increasing device complexity and manufacturing cost
Solution Approach 1:
The fan-out packaging structure creates a universal platform where the epoxy mold compound area serves as a standardized region for I/O terminals and wiring regardless of chip size. This allows the same wiring layout patterns to be used across different chip sizes, reducing design complexity and manufacturing costs while achieving compact packaging
Data Source
AI summary
A method of fabricating a semiconductor package is provided. The method may include: forming a first insulating film on a substrate which is at least partially provided with a semiconductor chip; forming a redistribution layer on the first insulating film; forming a solder crack control part, capable of controlling crack defects of a solder ball, on at least a portion of the redistribution layer; forming a second insulating layer on the redistribution layer and at least a portion of the first insulating film to expose a portion of the redistribution layer and the solder crack control part; and forming a solder ball on the redistribution layer exposed and the solder crack control part, wherein a top surface level of the solder crack control part may be formed to be relatively higher than a top surface level of the second insulating film.