Semiconductor Device With Segmented Solder Dams
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Solution Overview
Problem
Conventional semiconductor devices with a CoC (chip-on-chip) connection structure face issues where underfill resin flows onto external electrodes, inhibiting electrical contact and complicating size reduction and mass production, due to the need for precise resin control and potential dam delamination during heat treatment.
Innovation Solution
A semiconductor device with a CoC connection structure featuring dams that enclose multiple external electrodes, formed of solder, and an insulating film with openings, allowing resin to flow between chips while preventing overflow onto electrodes, and a method for producing such devices with solder dams and insulating films to ensure effective resin containment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dam is provided to prevent underfill resin from reaching external electrodes, then electrical contact is maintained, but the device size cannot be reduced and mass production is prevented
Solution Approach 1:
The dam structure is divided into multiple segments: a first dam portion extending from the internal electrode toward the external electrode, and a second dam portion extending from the external electrode toward the first dam portion. This segmentation allows the dam to effectively block resin while maintaining manufacturability and enabling mass production.
Solution Approach 2:
The dam structure is formed in advance before resin potting, with the first dam portion and second dam portion already positioned to prevent resin flow. This preliminary action ensures that subsequent mass production processes can proceed without additional resin control steps.
2Reliability
If the dam and upper semiconductor chip are located sufficiently far from each other to prevent resin overflow, then electrical contact is maintained, but size reduction is prevented
Solution Approach 1:
The dam structure provides localized resin containment precisely where needed - at the interface between the internal electrode and external electrode regions. This localized protection allows the overall device dimensions to be minimized while maintaining electrical contact reliability.
Solution Approach 2:
Instead of increasing the lateral distance between components to prevent resin overflow, the solution adds a vertical dimension with the dam structure rising from the substrate surface. This dimensional change blocks resin flow without increasing the device footprint.
3Reliability
If a single-line dam encloses internal electrodes, then resin containment is achieved, but delamination occurs during heat treatment or resin potting
Solution Approach 1:
The dam is segmented into a first dam portion and a second dam portion that are spatially separated and connected through the substrate. This segmentation distributes mechanical stresses and prevents delamination, as each portion is independently supported by the substrate.
Solution Approach 2:
The substrate acts as an intermediary that connects the first dam portion and second dam portion. This intermediate support structure prevents direct stress concentration at the dam-resin interface, eliminating delamination issues during heat treatment and potting.
Data Source
AI summary
A semiconductor device includes a rectangular lower semiconductor element; a plurality of external electrodes located in a pattern on the lower semiconductor element along sides thereof; a plurality of internal electrodes electrically connected to the plurality of external electrodes via a plurality of line patterns respectively and located on the lower semiconductor element in a pattern; dams provided in such a pattern that each of the dams encloses one or at least two external electrodes among the plurality of external electrodes; an upper semiconductor element mounted on the lower semiconductor element such that a plurality of terminals on the upper semiconductor element are electrically connected to the plurality of internal electrodes respectively; and a resin potted to flow to a space between the lower semiconductor element and the upper semiconductor element.