Semiconductor Source Contact Layout for Lower Charge Path Resistance
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Solution Overview
Problem
The integration of semiconductor devices is limited by the area occupied by unit memory cells, and existing three-dimensional semiconductor devices face challenges in operational reliability due to the complexity of stacking memory cells on a substrate.
Innovation Solution
A semiconductor device and manufacturing method that include a source structure with a cell region and a dummy region, featuring a first discharge contact structure and a second discharge contact structure of different depths, which are electrically connected through the source structure to reduce charge emission path resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional stacking of memory cells is implemented to improve integration, then the degree of integration is improved, but operational reliability deteriorates due to increased complexity
Solution Approach 1:
The patent divides the memory cell structure into multiple stacked layers (first memory cell layer and second memory cell layer) with distinct source structures and contact structures at different depths. This segmentation allows independent optimization of each layer's electrical characteristics while maintaining high integration through vertical stacking.
Solution Approach 2:
The patent implements different contact structure configurations for different regions: first discharge contact structures extending to the first source structure at specific depths, and second discharge contact structures extending to the second source structure at different depths. This local differentiation optimizes charge emission paths for each stacked layer while maintaining overall device reliability.
2Reliability
If contact structures are extended deeper into the source structure to reduce resistance, then charge emission path resistance is reduced, but device complexity increases
Solution Approach 1:
The discharge contact structures are segmented into multiple types based on depth: first discharge contact structures with first depth extending to the first source structure, and second discharge contact structures with second depth extending to the second source structure. This segmentation reduces resistance along charge emission paths while maintaining manageable device complexity through systematic differentiation.
Solution Approach 2:
The patent introduces depth as an additional dimension for contact structure configuration, with contact structures extending to different depths (first depth and second depth) within the stacked source structures. This dimensional approach optimizes electrical resistance by creating multiple charge emission paths at varying depths, reducing overall resistance without proportionally increasing complexity.
Data Source
AI summary
A semiconductor device, and a method for manufacturing the semiconductor device, includes a discharge interconnection structure and a source structure on the discharge interconnection structure. The semiconductor device also includes a first discharge contact structure extending through the source structure to be electrically connected to the discharge interconnection structure, the first discharge contact structure having a first depth. The semiconductor device further includes a second discharge contact structure positioned in the source structure, the second discharge contact structure having a second depth different from the first depth.