Semiconductor Source/Drain Contact Resistance Reduction
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Solution Overview
Problem
Current semiconductor processing methods face challenges in reducing contact resistance in FinFET devices, leading to decreased performance due to erosion of source and drain regions during the etch process.
Innovation Solution
A method involving the formation of a source/drain region, a doped semiconductor layer, and a metal silicide layer without breaking vacuum, followed by the deposition of a conductor, which reduces contact resistance by maintaining a higher dopant concentration and conformal coverage around the source/drain region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional processing methods are used to form source/drain contacts, then the etch process can create source/drain contact trenches, but the source and drain regions are eroded leading to increased contact resistance
Solution Approach 1:
A metal silicide layer is formed on the source/drain regions before the contact trench etch process. This preliminary formation of the silicide layer protects the source/drain regions from erosion during subsequent etching operations, thereby reducing contact resistance while preventing material loss
Solution Approach 2:
The metal silicide layer acts as a protective cushion layer formed beforehand on the source/drain regions. This cushioning layer prevents direct exposure of the source/drain regions to the etch process, thereby cushioning against erosion and maintaining low contact resistance
2Reliability
If the source/drain regions are exposed to the etch process, then contact trenches can be formed, but the regions are eroded decreasing device performance
Solution Approach 1:
The metal silicide layer serves as an intermediary protective layer between the etch process and the source/drain regions. This intermediary layer allows the etch process to proceed for trench formation while protecting the underlying source/drain regions from harmful erosion, thereby maintaining device performance
Solution Approach 2:
The metal silicide layer, which would normally be an additional material step, is converted into a beneficial protective element. The etch process that would normally harm the source/drain regions is instead used to selectively remove dielectric material while the silicide layer protects the source/drain regions, converting a potentially harmful process into a beneficial selective etch
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively decreases contact resistance in semiconductor devices, enhancing their performance by maintaining a higher dopant concentration and conformal coverage, applicable to both planar and three-dimensional transistor devices.
Implementation Method 1
forming a metal silicide layer on the doped semiconductor layer
Implementation Method 2
maintaining a higher dopant concentration
Data Source
AI summary
The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing chamber. The method includes forming a source/drain region in a processing system, forming a doped semiconductor layer on the source/drain region in the processing system, forming a metal silicide layer, forming a dielectric material, forming a trench in the dielectric material, and filling the trench with a conductor. The source/drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking vacuum. A semiconductor device includes a plurality of layers, and the semiconductor device has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device. Embodiments of the present disclosure enable formation of a source/drain contact with reduced contact resistance by using integrated processes, which allows various operations of the source/drain contact formation to be performed within the same processing system.