Semiconductor Device Source Drain Contact Doping

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Solution Overview

Problem

Conventional semiconductor devices, such as planar MOS transistors and FinFETs, face challenges with poor control over channel current and significant leakage current, leading to inefficiencies in signal production and transmission.

Innovation Solution

A semiconductor device fabrication method involving the formation of gate structures on a base substrate, with source/drain doped regions having recessed top surfaces and additional contact doped regions formed by doping with ions of the same conductivity type, which reduces resistance and alleviates current crowding effects by increasing the contact area with conducting plugs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional planar MOS transistor structure is used, then manufacturing is simple, but channel current control ability is poor and leakage current is serious

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidchannel current control ability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The source and drain regions are segmented into two distinct parts: source/drain doped regions extending into the substrate for current control, and separate contact doped regions at the surface for electrical contact. This segmentation allows each region to be optimized independently - the doped regions provide strong channel control while the contact regions provide low-resistance contacts, resolving the contradiction between manufacturing simplicity and device performance.

Inventive Principle:
Principle #1Segmentation

2Reliability

If FinFET structure is used, then channel current control ability is improved, but leakage current remains serious and device performance is still poor

Engineering Contradiction:
Improvechannel current control abilityVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

Different doping concentrations are applied to different locations: high doping concentration in the contact doped regions to reduce contact resistance and suppress leakage, and appropriate doping in the source/drain doped regions for channel control. This local quality differentiation allows the device to achieve both good channel control and low leakage current simultaneously.

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If source/drain regions are formed without contact doped regions, then manufacturing process is simple, but resistance is high and current crowding occurs

Engineering Contradiction:
Improveprocess simplicityVSAvoidcontact resistance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

Contact doped regions are formed preliminarily during the same fabrication process as the source/drain doped regions, rather than as a separate subsequent step. The contact regions are doped with high concentration ions in advance to create low-resistance contact areas, which eliminates current crowding effects and reduces overall device resistance without significantly complicating the manufacturing process.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enhances the control over channel current and reduces leakage current, improving the overall performance of semiconductor devices by increasing the contact area and reducing resistance in the source/drain regions.

Implementation Method 1

doping into the top surfaces of the source/drain doped regions with contact ions to form contact doped regions

Methodology Applied
Scientific EffectIon doping: Ion Implantation

Data Source

PatentUS10446652B2Semiconductor device and fabrication method thereof
Publication Date: 2019.10.15 SEMICON MFG INT (SHANGHAI) CORP
  • US10446652B2 patent drawing
  • US10446652B2 patent drawing
  • US10446652B2 patent drawing

AI summary

Semiconductor device and fabrication method are provided. The method includes: providing a base substrate; forming gate structures on the base substrate; forming source/drain doped regions in the base substrate on sides of each gate structure, where the source/drain doped regions have recessed top surfaces and are doped with source/drain ions; and doping into the recessed top surfaces of the source/drain doped regions with contact ions to form contact doped regions in top portions of the source/drain doped regions, where the contact ions have a conductivity type same as the source/drain ions.