Semiconductor Source/Drain Contact Resistance Reduction
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Solution Overview
Problem
As semiconductor devices undergo miniaturization, the increasing complexity of integrating more components into smaller areas leads to challenges such as elevated source/drain contact resistance, which affects the electrical performance of devices like NSFETs and FinFETs.
Innovation Solution
The formation of source/drain contacts that extend into epitaxial source/drain regions, utilizing a two-cycle plasma etching process to create recesses that reduce the distance between these contacts and channel regions, thereby lowering contact resistance and improving electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If source/drain contacts are formed at the surface level, then the manufacturing process is simpler, but the contact resistance increases due to longer current path distance
Solution Approach 1:
The patent transitions from surface-level contact formation to vertical contact formation by etching recesses into the epitaxial source/drain regions. This dimensional change allows contacts to reach deeper into the material, reducing the current path distance and contact resistance while maintaining manufacturing feasibility through controlled etching processes
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated, but contact resistance increases due to scaled-down dimensions
Solution Approach 1:
As device dimensions are scaled down to increase integration density, the patent compensates for increased contact resistance by forming vertical recesses that extend the contact depth. This vertical dimension approach maintains effective contact area and reduces resistance even when lateral dimensions are reduced
Solution Approach 2:
The patent modifies the contact formation parameters by changing from horizontal surface contacts to vertical depth-based contacts. This parameter change allows optimization of contact resistance independent of the scaled-down lateral feature sizes, enabling continued miniaturization without sacrificing electrical performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces source/drain contact resistance and enhances the electrical performance of semiconductor devices by minimizing the distance between source/drain contacts and channel regions, improving the overall functionality of NSFETs and FinFETs.
Implementation Method 1
utilizing a two-cycle plasma etching process to create recesses that reduce the distance between these contacts and channel regions
Data Source
AI summary
A semiconductor device including source/drain contacts extending into source/drain regions, below topmost surfaces of the source/drain regions, and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a first gate stack over the semiconductor substrate and surrounding four sides of the first channel region; a first epitaxial source/drain region adjacent the first gate stack and the first channel region; and a first source/drain contact coupled to the first epitaxial source/drain region, a bottommost surface of the first source/drain contact extending below a topmost surface of the first channel region.