Semiconductor Device Source Drain Diffusion Depth Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices face issues with punch-through and increased on-resistance due to reduced gate length, leading to lower ESD and latch-up tolerance, and require additional mask steps increasing costs when forming separate N-type and P-type source/drain regions.
Innovation Solution
A semiconductor device structure where the N-type and P-type source/drain regions are formed with specific diffusion depths and impurity concentrations, allowing for simultaneous formation of low concentration source regions and MOSFET source/drain regions, and a substrate contact region is placed under the low concentration source region to maintain high ESD and latch-up tolerance without increasing process costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the gate length is reduced to shrink the peripheral circuit, then the area of the peripheral circuit is reduced, but punch-through occurs and ESD and latch-up tolerance are lowered
Solution Approach 1:
The patent applies local quality by forming a deep N-type substrate contact region (115a) specifically under the N-type low concentration source region (105b) with a diffusion depth greater than the gate length, while keeping other regions unchanged. This localized modification provides ESD and latch-up protection only where needed, without affecting the overall circuit shrinkage
Solution Approach 2:
The patent extends the solution into the depth dimension by forming a substrate contact region with a diffusion depth greater than the gate length, rather than trying to solve the problem in the planar dimension. This vertical extension provides the necessary protection while maintaining the reduced gate length in the horizontal plane
2Manufacturing precision
If separate mask steps are used to form N-type and P-type source/drain regions, then the manufacturing precision is improved, but the device complexity and process costs increase
Solution Approach 1:
The patent merges the formation of N-type low concentration source regions (105b) and P-type substrate contact regions (115a) into a single ion implantation step, eliminating the need for separate mask steps. The merging is achieved by using a common mask pattern that defines both regions simultaneously, reducing process complexity while maintaining manufacturing precision
Solution Approach 2:
The single ion implantation step serves multiple functions: forming both the N-type low concentration source regions and the P-type substrate contact regions in one operation. This multi-functional approach eliminates redundant process steps and reduces overall device fabrication complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach suppresses the increase in on-resistance and maintains high ESD and latch-up tolerance while reducing process costs by allowing the formation of source/drain regions in the same step, without the need for additional mask steps.
Implementation Method 1
the N-type low concentration source region (105b) and the P-type substrate contact region (115a) are formed in the same step
Data Source
AI summary
A high-voltage transistor and a peripheral circuit including a second conductivity type MOSFET are provided together on a first conductivity type semiconductor substrate. The high-voltage transistor includes: a low concentration drain region of a second conductivity type formed in the semiconductor substrate; a low concentration source region of a second conductivity type formed in the semiconductor substrate and spaced apart from the low concentration drain region; and a high concentration source region of a second conductivity type having a diffusion depth deeper than that of the low concentration source region. A diffusion depth of the low concentration source region is equal to that of source/drain regions of the MOSFET.