Semiconductor Source Drain Regions With Multi-Layer Epitaxial Patterns

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Solution Overview

Problem

The scaling-down of MOS transistors in semiconductor devices leads to degradation in operational characteristics, necessitating techniques to enhance the performance of highly integrated semiconductor devices.

Innovation Solution

The semiconductor device incorporates an active pattern with source/drain regions featuring a first epitaxial pattern inducing tensile strain and a second epitaxial pattern with reduced surface roughness, made of materials with different lattice constants, to improve channel region mobility and surface smoothness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If MOS transistors are scaled down to increase integration density, then the degree of integration is improved, but operational characteristics deteriorate

Engineering Contradiction:
Improveintegration densityVSAvoidoperational characteristics
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The source/drain region is divided into multiple epitaxial patterns with different materials and properties at different locations. The first epitaxial pattern has a lattice constant matching the substrate, while the second epitaxial pattern has a larger lattice constant, creating local variations in strain and electrical properties to improve carrier mobility without compromising device reliability

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The source/drain region is formed as a composite structure comprising multiple epitaxial patterns made of different materials. This composite structure combines the advantages of each material - the first epitaxial pattern provides lattice matching with the substrate while the second epitaxial pattern introduces beneficial strain effects to enhance carrier mobility in the channel region

Inventive Principle:
Principle #40Composite materials

2Ease of manufacture

If a single epitaxial pattern is used in source/drain regions, then manufacturing is simpler, but carrier mobility is insufficient

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidcarrier mobility
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

Different epitaxial patterns are placed in specific locations within the source/drain region. The first epitaxial pattern contacts the active pattern and provides a foundation, while the second epitaxial pattern is positioned to induce strain in the channel region, optimizing carrier mobility where it is most needed

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The lattice constant parameter is varied across different epitaxial patterns. The first epitaxial pattern has a lattice constant matching the substrate, while the second epitaxial pattern has a larger lattice constant to induce tensile strain in the channel region, thereby enhancing carrier mobility

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If the outer surface of epitaxial patterns is rough, then manufacturing may be easier, but electrical performance is degraded

Engineering Contradiction:
Improvesurface formation easeVSAvoidelectrical performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The second epitaxial pattern is specifically engineered to have a smooth outer surface at the boundary with the first epitaxial pattern. This smooth surface is critical for maintaining good electrical contact and reducing scattering effects, thereby preserving electrical performance while the internal structure provides strain benefits

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the mobility of majority carriers and reduces surface roughness, thereby improving the electrical performance and reliability of the semiconductor device.

Implementation Method 1

a first epitaxial pattern inducing tensile strain

Methodology Applied
Scientific EffectTensile strain: Elasticity

Implementation Method 2

a second epitaxial pattern with reduced surface roughness

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS10756211B2Semiconductor devices including source/drain regions having multiple epitaxial patterns
Publication Date: 2020.08.25 SAMSUNG ELECTRONICS CO LTD
  • US10756211B2 patent drawing
  • US10756211B2 patent drawing
  • US10756211B2 patent drawing

AI summary

A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.