Semiconductor Device Source Extraction Via Structures
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Solution Overview
Problem
In high-frequency power amplifiers, increasing the gate width of field effect transistors (FETs) to enhance output and efficiency leads to challenges in optimizing the distance between the source and via holes, resulting in degraded high-frequency characteristics and phase differences among output signals, which limits the amplifier's performance.
Innovation Solution
A semiconductor device design featuring FETs with multiple gates and sources arranged in parallel, where source extractions are connected through via structures with equal lengths to an upper electrode, allowing for optimized inductance and reduced parasitic inductance, thereby improving signal phase alignment and output efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the gate width of FET is increased to increase operating current and output, then the efficiency and output of power amplifier are improved, but the distance between source and via hole cannot be optimized, resulting in degraded high frequency characteristic
Solution Approach 1:
The patent transitions from a planar substrate back-surface via hole connection to a three-dimensional structure where the reference potential layer is moved to the substrate surface, allowing via holes to connect vertically from the surface rather than passing through the substrate thickness. This dimensional change enables optimized via hole positioning and length for high-frequency performance while maintaining large gate width FETs.
Solution Approach 2:
The patent inverts the conventional structure by placing the reference potential layer on the substrate surface instead of on the back surface. This inversion allows the via holes to connect the source to the reference potential layer immediately above or near the source region, optimizing the inductance and high-frequency characteristics while enabling large gate width FETs.
2Productivity
If the number of fingers of gate is increased to secure large gate width, then the operating current is increased, but the inductance of interconnection between each source and via hole becomes different, making it difficult to optimize
Solution Approach 1:
The patent creates equipotential conditions by providing a continuous reference potential layer on the substrate surface that all via holes connect to at the same potential level. This ensures that despite having multiple fingers and sources, all interconnections have equal inductance characteristics, enabling easy optimization and maintaining signal integrity across all FET fingers.
Solution Approach 2:
The patent segments the large gate width FET into multiple fingers with multiple sources, each connected to the reference potential layer through individual via holes. By combining segmentation with the surface-mounted reference potential layer, each finger can be independently optimized while maintaining equal inductance across all segments.
3Reliability
If unit FETs are arrayed in parallel with one or two sources to fix interconnection length, then the high frequency characteristic is prevented from degrading, but the number of via holes increases, making the element size large
Solution Approach 1:
The patent merges multiple via holes into a shared reference potential layer structure on the substrate surface. Instead of having separate via holes for each unit FET that are spaced apart, all via holes connect to the same continuous reference potential layer, allowing compact arrangement and reducing the overall element size while maintaining equal inductance and high-frequency characteristics.
4Ease of manufacture
If via structure is provided immediately above source region to make inductance zero, then the connection is simplified, but the inductance cannot be optimized to stabilize circuit
Solution Approach 1:
The patent changes the inductance parameter from zero (immediate above source) to an optimized non-zero value by positioning via holes at optimal distances from the source region and connecting them to a surface-mounted reference potential layer. This parameter optimization stabilizes the circuit while maintaining manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design ensures equal inductance for all sources, stabilizes the circuit characteristics, and maximizes output by aligning signal phases, resulting in enhanced high-frequency performance and reduced device size.
Implementation Method 1
a plurality of source extractions each connected to respective sources through via structures passing the insulating layer and to the upper electrode
Implementation Method 2
the inductance that the interconnection between each source and the via hole has is also different for each source... This design ensures equal inductance for all sources
Data Source
AI summary
A semiconductor device is disclosed. The semiconductor comprises a field effect transistor (FET) provided in a substrate, the FET including a plurality of gates, sources, and drains each extending in parallel along a longitudinal direction of the gates, the sources, and the drains; an upper electrode provided above the substrate with an insulating layer therebetween, the upper electrode having an opening where the FET is disposed, and a plurality of source extractions each connected to respective sources through via structures passing the insulating layer and to the upper electrode, the source extractions extending along the longitudinal direction.