Semiconductor Source Field Plate Recess Design
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Solution Overview
Problem
The use of source field plates in semiconductor devices increases gate-source capacitance, deteriorating frequency characteristics and reducing breakdown voltage, while attempts to reduce this capacitance by shrinking the source field plate area delay frequency response and affect device reliability.
Innovation Solution
A semiconductor device design featuring a dielectric layer with recesses to reduce gate-source capacitance, allowing for increased thickness of the dielectric layer while maintaining effective electric field modulation by the source field plate, thereby enhancing breakdown voltage and frequency characteristics without compromising device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If source field plates are used to increase breakdown voltage, then breakdown voltage is improved, but gate-source capacitance increases which deteriorates frequency characteristics
Solution Approach 1:
The patent applies local quality by creating a recess structure at a specific location (under the source field plate) to modify the electric field distribution locally. This allows the source field plate to maintain its voltage-blocking function while reducing its capacitive effect on the gate, thereby resolving the contradiction between improving breakdown voltage and maintaining frequency characteristics.
2Reliability
If area of source field plate overlapping gate electrode is reduced to decrease gate-source capacitance, then gate-source capacitance is reduced, but frequency response is delayed and frequency characteristics are affected
Solution Approach 1:
The patent resolves this contradiction by transitioning from a two-dimensional area reduction approach to a three-dimensional structural modification. By creating a recess (adding vertical dimension) rather than simply reducing the horizontal area, the patent maintains adequate overlapping area for frequency response while reducing capacitance through the altered electric field distribution in the recess region.
3Reliability
If dielectric layer thickness is increased to reduce gate-source capacitance, then gate-source capacitance is reduced, but electric field modulation by source field plate is weakened
Solution Approach 1:
The patent applies local quality by creating a recess structure at a specific location (under the source field plate) to modify the electric field distribution locally. This allows the source field plate to maintain its voltage-blocking function while reducing its capacitive effect on the gate, thereby resolving the contradiction between improving breakdown voltage and maintaining frequency characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces gate-source capacitance, increases breakdown voltage, and improves frequency characteristics, maximizing high output power without affecting device frequency response.
Implementation Method 1
distribution of the electric field lines in the depletion region of a barrier layer is modulated by using the field plate
Implementation Method 2
use of source field plates may increase the breakdown voltage of devices, but it increases gate-source capacitance Cgs of devices
Implementation Method 3
quantum wells and two-dimensional electron gas with high concentration can be generated near heterojunction interfaces, such two-dimensional electron gas is trapped in the quantum wells
Implementation Method 4
carriers and ionized impurities are separated in space, thereby reducing Coulomb force of the ionized impurities against the carriers
Implementation Method 5
distribution of the electric field lines in the depletion region of a barrier layer is modulated by using the field plate, the leakage current of the gate electrode is reduced
Data Source
AI summary
A semiconductor device is disclosed, comprising: a substrate; a semiconductor layer disposed on the substrate; a source electrode and a drain electrode disposed on the semiconductor layer, and a gate electrode disposed between the source electrode and the drain electrode; a dielectric layer disposed on at least a part of the surface of the semiconductor layer which is between the gate electrode and the drain electrode, the dielectric layer having at least a recess therein; and a source field plate disposed on the dielectric layer and at least partially covering the recess, the source field plate being electrically connected to the source electrode through at least a conductive path. A method of manufacturing such a semiconductor device is also disclosed.