Semiconductor Source Region Gapfill Patterns for On-Resistance Reduction
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Solution Overview
Problem
In the semiconductor industry, there is a challenge in achieving high integration density, multi-functionalization, high speed, reproducibility, and reliability of semiconductor devices due to trade-offs between these characteristics, particularly in reducing on-resistance without compromising breakdown voltage.
Innovation Solution
A semiconductor device design that includes gapfill patterns in the source region to exert compressive stress on the channel region between the source and drain regions, using materials like silicon oxide or silicon germanium to fill trenches, which helps increase hole mobility and reduce on-resistance without significant changes in other electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the feature size and distance of semiconductor patterns are decreased to increase integration density, then the operation speed and reliability of semiconductor devices deteriorate
Solution Approach 1:
The patent applies local quality by introducing gapfill patterns specifically in the source region rather than uniformly across the entire device. This localized approach allows the source region to have enhanced properties (compressive stress, higher hole mobility) while other regions maintain their original characteristics, thus improving device performance without requiring overall size increases that would reduce integration density.
Solution Approach 2:
The patent changes physical parameters by introducing compressive stress through gapfill patterns, which modifies the hole mobility parameter in the source region. This parameter change enables higher operating speeds and improved reliability without increasing the physical dimensions of the device, thereby resolving the contradiction between integration density and device performance.
2Reliability
If the channel width is increased to reduce on-resistance, then the device area and integration density deteriorate
Solution Approach 1:
The patent changes the stress parameter in the source region through gapfill patterns, which increases hole mobility and effectively reduces on-resistance without increasing the physical channel width. This parameter change allows maintaining small device area for high integration density while achieving low on-resistance through improved carrier transport properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces on-resistance of high voltage transistors while maintaining or improving breakdown voltage, enhancing the overall performance and reliability of semiconductor devices.
Implementation Method 1
the gapfill patterns may be configured to exert a compressive stress on a channel region between the source and drain regions
Data Source
AI summary
Semiconductor devices are provided. A semiconductor device includes a substrate including a well region. The semiconductor device includes a source region in the well region. The semiconductor device includes a drain region. The semiconductor device includes a gate electrode that is between the source and drain regions, when viewed in a plan view. Moreover, the semiconductor device includes first and second patterns, in the source region, that are spaced apart from each other when viewed in the plan view.