Semiconductor Source Pad Segmentation for Low Resistance

Solution Overview

Problem

Field effect transistors face challenges in minimizing electrical interference and resistance while maintaining low capacitance due to the design of source and drain pads, which affects their performance in semiconductor devices.

Innovation Solution

The semiconductor device incorporates a specific arrangement of source and drain electrodes, traces, vias, and pads with dielectric layers and metal structures that reduce resistance and capacitance by optimizing the layout and connections between these components, ensuring that the source and drain branches do not overlap, thereby minimizing electrical interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If source and drain pads are designed with large bonding areas to facilitate external circuit bonding, then ease of connection is improved, but electrical interference and resistance between source and drain increase

Engineering Contradiction:

Improveease of connectionVSAvoidelectrical interference

Core Design Contradiction:

Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The source pad is segmented into multiple source electrodes (first source electrode, second source electrode, etc.) arranged in sequence along the first direction. This segmentation allows each electrode to have optimized dimensions and positioning, reducing the overall capacitance between source and drain while maintaining adequate bonding area through the collective arrangement of multiple electrodes.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a multi-dimensional layout where source and drain electrodes are arranged not only along the first direction but also positioned at different locations in the planar structure. The source electrodes are positioned to extend along the first direction while drain electrodes are arranged to minimize overlap, utilizing spatial distribution to reduce capacitance while maintaining bonding capability.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If source and drain electrodes are positioned closer to reduce device area, then device compactness is improved, but resistance and electrical interference increase

Engineering Contradiction:

Improvedevice areaVSAvoidresistance

Core Design Contradiction:

Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The source electrodes and drain electrodes are designed with asymmetric positioning and dimensional characteristics. The source electrodes extend along the first direction with specific lengths and spacings that are optimized independently from the drain electrode configuration. This asymmetric design allows compact arrangement while controlling the resistance and capacitance characteristics through non-uniform spacing and positioning.

Inventive Principle:

Principle #4Asymmetry

Solution Approach 2:

Different regions of the electrode structure are assigned different properties: the source electrodes have optimized dimensions and spacing for low resistance connection, while the drain electrodes are positioned to minimize capacitance coupling. The dielectric layer thickness and material properties are also optimized locally in different regions to achieve the desired electrical characteristics.

Inventive Principle:

Principle #3Local quality

3Area of stationary object

If source and drain electrodes are positioned closer to reduce device area, then device compactness is improved, but electrical interference and capacitance increase

Engineering Contradiction:

Improvedevice areaVSAvoidcapacitance

Core Design Contradiction:

Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The source pad is segmented into multiple source electrodes (first source electrode, second source electrode, etc.) arranged in sequence along the first direction. This segmentation allows each electrode to have optimized dimensions and positioning, reducing the overall capacitance between source and drain while maintaining adequate bonding area through the collective arrangement of multiple electrodes.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a multi-dimensional layout where source and drain electrodes are arranged not only along the first direction but also positioned at different locations in the planar structure. The source electrodes are positioned to extend along the first direction while drain electrodes are arranged to minimize overlap, utilizing spatial distribution to reduce capacitance while maintaining bonding capability.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9324819B1Semiconductor device

Publication Date: 2016.04.26 ANCORA SEMICON INC

AI summary

A semiconductor device includes an active layer, source electrodes, drain electrodes, gate electrodes, a first dielectric layer, source trace, first source vias, a second dielectric layer, a source pad, and second source vias. The first dielectric layer covers the source electrodes, the drain electrodes, and the gate electrodes. The source traces are disposed on the first dielectric layer, are electrically connected to the source electrodes, and are covered by the second dielectric layer. The source pad is disposed on the second dielectric layer, and includes a first source trunk, a first source branch, and a source sub-branch. The first source branch is protruded from the first source trunk and is electrically connected to one of the drain traces through the second source vias. The source sub-branch is protruded from the first source branch and is electrically connected one of the source electrodes through the third source vias.