3D Semiconductor Source Select Line Segmentation for Erase Reliability
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Solution Overview
Problem
Current three-dimensional (3D) semiconductor devices face challenges in enhancing operation reliability, particularly in the manufacturing process, where achieving stable erase operations and ensuring reliable electrical connections between the channel layer and source structure are difficult due to limitations in the design of source select lines and word lines.
Innovation Solution
The semiconductor device incorporates a source select line with a first and second conductive layer, where the channel layer passes through the word lines and source select line, and a contact source layer is formed to ensure direct contact with the channel layer, improving electrical connectivity and stability during erase operations by expanding the source junction to overlap the source select line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional 3D semiconductor device structure is used with single-layer source select line, then the device complexity is reduced and manufacturing is easier, but the operation reliability and electrical connection stability are insufficient
Solution Approach 1:
The source select line is divided into multiple conductive layers (first conductive layer and second conductive layer) stacked vertically, with each layer serving specific functional purposes. This segmentation allows independent optimization of electrical connection and select control functions, improving overall reliability while managing complexity through functional division
Solution Approach 2:
The source select line transitions from a planar single-layer structure to a vertical multi-layer stacked structure. By adding the vertical dimension with multiple conductive layers, the device achieves improved electrical connection stability and GIDL current generation without significantly increasing lateral device complexity
2Reliability
If the channel layer is confined within the word lines without protrusion, then the manufacturing precision is easier to control, but the electrical connection between channel layer and source structure is unreliable
Solution Approach 1:
The channel layer is designed to protrude toward the lower direction than the source select line in advance, creating a predetermined overlap region with the source structure. This preliminary geometric configuration ensures reliable electrical connection before actual device operation, while the protrusion distance is controlled within manufacturable limits
Solution Approach 2:
The channel layer protrusion is nested within the overlap region between the source select line and source structure, creating a hierarchical spatial relationship. The protruding channel layer portion is positioned within the vertical projection of the source structure, ensuring reliable electrical connection while maintaining manufacturing control
3Reliability
If the source junction is not expanded to overlap the source select line, then the device structure is simpler, but the erase operation reliability is insufficient
Solution Approach 1:
The source junction is expanded vertically to create an overlap region with the source select line, transitioning from a lateral to a vertical spatial relationship. This vertical expansion in the third dimension enables reliable erase operations through improved GIDL current generation without significantly increasing lateral device complexity
Solution Approach 2:
The source junction overlap region merges the source structure and channel layer protrusion within the vertical projection of the source select line. This merging creates a unified functional region that simultaneously achieves electrical connection and erase operation reliability
Data Source
AI summary
A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include a source select line. The semiconductor device may include word lines. The semiconductor device may include a channel layer. The semiconductor device may include a source structure. The source structure may be disposed under the source select line. The source structure may be in contact with the channel layer.