Semiconductor Device Source Wiring Substructures for Insulation Testing
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Solution Overview
Problem
Current methods for testing semiconductor devices are inefficient in detecting insulation layer defects, leading to increased costs and efforts in identifying manufacturing errors.
Innovation Solution
The implementation of a semiconductor device design with first and second source wiring substructures connected to source doping region portions and source field electrodes, respectively, allows for a temporary test measurement by applying a test voltage and measuring leakage current, thereby improving testability and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional testing methods are used for insulation layer defects, then manufacturing errors can be detected, but the testing process is inefficient and costly
Solution Approach 1:
The patent implements preliminary action by providing test contacts and wiring substructures during the manufacturing process itself, rather than performing separate post-manufacturing tests. The test contacts are formed in the same wiring layers as the functional contacts, and the wiring substructures are created using the same fabrication steps, enabling insulation tests to be conducted inline during production without requiring additional manufacturing steps or separate testing equipment.
2Difficulty of detecting and measuring
If separate test structures are added to the semiconductor device, then insulation testing becomes possible, but the device complexity increases
Solution Approach 1:
The patent merges the test structure with the functional structure by using the same wiring layers, contact holes, and manufacturing processes for both test and operational elements. The first and second wiring substructures are formed using identical fabrication steps as the functional wiring, and the test contacts share the same physical and chemical properties as the functional contacts. This integration eliminates the need for separate test structures and reduces overall device complexity.
Solution Approach 2:
The wiring substructures serve dual functions: they provide electrical connections for normal device operation and simultaneously serve as test structures for insulation measurements. The first wiring substructure connects to source regions for both operation and testing, while the second wiring substructure connects to field electrodes for both operation and testing. This multi-functionality eliminates the need for dedicated test-only structures and reduces device complexity.
3Manufacturing precision
If front-end tests are performed for insulation quality, then manufacturing errors can be detected early, but the testing costs increase significantly
Solution Approach 1:
The patent implements self-service by enabling the semiconductor device to perform its own insulation testing through integrated test contacts and wiring substructures that are part of the device itself. The testing can be conducted using standard equipment without requiring specialized front-end testing facilities, allowing manufacturers to perform insulation quality checks inline during production at lower cost and with simpler infrastructure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables effective testing of insulation layer quality without the need for costly front-end tests, improving testability and reducing efforts and costs associated with detecting defects.
Implementation Method 1
The first source wiring substructure is electrically insulated from the second source wiring substructure in the wiring layer
Implementation Method 2
measuring a leakage current between the first source wiring substructure and the second source wiring substructure caused by the applied test voltage
Data Source
AI summary
A semiconductor device includes a first source wiring substructure connected to a plurality of source doping region portions of a transistor structure, and a second source wiring substructure connected to a plurality of source field electrodes located in a plurality of source field trenches extending into a semiconductor substrate. A contact wiring portion of the first source wiring substructure and a contact wiring portion of the second source wiring substructure are located in a wiring layer of a layer stack located on the semiconductor substrate. The contact wiring portion of the first source wiring substructure and the contact wiring portion of the second source wiring substructure each have a lateral size sufficient for a contact for at least a temporary test measurement. The wiring layer including the contact wiring portions is located closer to the substrate than any ohmic electrical connection between the first and the second source wiring substructures.