Semiconductor Space Stitching via Double Exposure
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Solution Overview
Problem
Conventional semiconductor lithographic processes struggle to achieve tight tolerance in stitching spaces, resulting in perceptible errors and jogs at smaller feature sizes, particularly below 0.32 um, due to single slit diffraction issues and lack of precision in aligning image fields.
Innovation Solution
A novel lithographic technique that stitches two spaces together using a double exposure method with intentional offset in the x- and y-directions, allowing for improved overlay tolerance and tighter control of space width, comparable to unstitched lines, by applying a double light exposure dose to the overlapped space regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single exposure stitching is used for spaces, then the process is simple, but the stitching precision deteriorates with perceptible errors at smaller feature sizes
Solution Approach 1:
The patent divides the stitching process into two separate exposure steps: a first exposure that prints the space feature, and a second exposure that prints an overlapping image field containing the same space feature. This segmentation allows each exposure to be optimized independently, with the second exposure providing corrective alignment to achieve tighter stitching tolerances without requiring complete process redesign
Solution Approach 2:
The first exposure is performed preliminarily to establish the base space feature pattern. Then, a second exposure is applied with intentional overlap and slight misalignment, where the space feature from the first exposure acts as a preliminary structure that guides the alignment of the second exposure. This preliminary action enables the subsequent exposure to focus solely on achieving precise stitching alignment
2Manufacturing precision
If double exposure with overlap is used for spaces, then the stitching tolerance improves, but the process complexity increases
Solution Approach 1:
The space feature itself serves as the alignment reference for the double exposure process. The first exposure creates the space feature that then acts as the registration target for the second exposure, eliminating the need for separate alignment marks or external referencing systems. The process uses its own output as the alignment guide, reducing the complexity of alignment infrastructure
Solution Approach 2:
The patent intentionally introduces controlled parameter changes between the two exposures: a slight offset in positioning (intentional misalignment) and overlapping exposure regions. By deliberately changing these parameters rather than maintaining identical positioning, the process achieves tighter effective stitching tolerances through the superposition of two exposures with controlled variations
3Length of moving object
If spaces are stitched at smaller feature sizes, then the device scaling improves, but the stitching error increases due to single slit diffraction
Solution Approach 1:
The patent applies partial action by using only a portion of the total possible overlap region for the critical space feature alignment. The overlapping area is designed to be sufficient for achieving the required precision without requiring complete coverage, thereby reducing the cumulative diffraction effects that would occur with larger overlap regions while still achieving the necessary stitching accuracy for scaled-down features
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This technique enhances the tolerance of stitched spaces to match or exceed that of unstitched lines, achieving seamless stitching and improved control for feature sizes down to 180 nm technology, reducing errors and standard deviation in space width measurements.
Implementation Method 1
circuits, which may comprise electronic devices including active and passive elements interconnected by one or more conductors (lines), are typically formed by successively imprinting patterns onto a semiconductor wafer utilizing one or more photolithographic masks, and performing series of etches and depositions of materials that form on and/or react with the wafer
Implementation Method 2
This is driven by interference from the light from each edge of the isolated line that is not possible with an isolated space that is essentially single slit diffraction
Data Source
AI summary
A method for manufacturing a stitched space in a semiconductor circuit implements a photolithographic process for printing one or more image fields on a wafer surface, each image field corresponding to a portion of a circuit or device and including a space that is to be stitched in adjacent image fields. The space to be stitched that is produced from an image field is overlapped onto the space to be stitched produced from the adjacent image field, however, the overlapped space from the adjacent image fields is intentionally misaligned. The stitched space is then subject to the double light exposure dose to print the stitched space, with the result that an overlay tolerance of the stitched space is improved.