Semiconductor Structure with Spaced Supporters for 3DIC
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Solution Overview
Problem
The integration density of semiconductor components is limited by physical constraints such as the minimum size of components and increased interconnections, leading to RC delay and power consumption issues in two-dimensional integrated circuits, prompting the need for three-dimensional integrated circuits (3DIC) with effective stacking and connection methods.
Innovation Solution
A semiconductor structure featuring a semiconductor unit with bonding structures and supporters, where the supporters are metal or polymer blocks spaced apart from the bonding structures, allowing for reduced parasitic capacitance and increased signal transmission speed through the use of insulation layers and reflow processes to maintain mechanical support and adherence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conductive lines are placed close together to increase integration density, then the number of components per area increases, but parasitic capacitance increases and signal transmission speed decreases
Solution Approach 1:
The patent introduces a vertical dimension by placing supporter structures between bonding structures in the Z-direction, allowing conductive lines to be spaced apart vertically while maintaining high horizontal integration density. This dimensional approach reduces parasitic capacitance between adjacent conductive lines without sacrificing the quantity of components per area.
2Object-affected harmful factors
If conductive lines are spaced apart to reduce parasitic capacitance, then signal transmission speed improves, but integration density decreases
Solution Approach 1:
The supporter structures are nested between the bonding structures, utilizing the vertical space efficiently. Multiple functional elements (supporters, bonding structures, conductive lines) are arranged in a nested configuration where supporters are positioned in the gaps between bonding structures, maximizing space utilization while maintaining proper spacing for reduced capacitance.
3Adaptability or versatility
If more interconnections are added to increase device functionality, then the circuit capabilities improve, but RC delay and power consumption increase
Solution Approach 1:
By utilizing the vertical dimension with supporter structures, the patent enables better routing and spacing of interconnections in three-dimensional space. This allows for optimized signal paths that reduce RC delay while maintaining comprehensive circuit functionality, as conductors can be positioned to minimize resistance and capacitance effects without limiting the number or complexity of interconnections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces parasitic capacitance and enhances signal transmission speed in 3DIC structures by separating conductive lines with insulation layers and maintaining mechanical support through the use of polymer supporters that soften and adhere during reflow, improving the yield and efficiency of 3DIC manufacturing.
Implementation Method 1
polymer supporters that soften and adhere during reflow
Implementation Method 2
polymer supporters that soften and adhere during reflow
Implementation Method 3
reduces parasitic capacitance and enhances signal transmission speed in 3DIC structures by separating conductive lines with insulation layers
Data Source
AI summary
The present disclosure relates to a semiconductor structure. The semiconductor structure includes a semiconductor unit, one or more bonding structures, and at least one supporter. The semiconductor unit includes at least one via. The one or more bonding structures are disposed over the semiconductor unit and electrically connected to the at least one via. The at least one supporter is disposed over the semiconductor unit. The at least one supporter is a metal block or a polymer block spaced apart from the one or more bonding structures.