Semiconductor Device Spacer Board Power Ground Capacitance
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Solution Overview
Problem
In semiconductor memory devices, existing structures struggle to sufficiently reduce voltage fluctuation noise between the power supply and ground due to limitations in increasing capacitance between the power supply and ground layers, which hinders the reduction of impedance at high frequencies as the device speed increases.
Innovation Solution
A semiconductor device configuration that includes a wiring board with a spacer board having power supply and ground conductor layers, where the first semiconductor chips are mounted on the spacer board and connected to the power supply and ground conductor layers, allowing for increased capacitance between the power supply and ground, thereby reducing impedance and voltage fluctuation noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitance between power supply and ground is increased by using ground conductor layer and power supply conductor layer within chip thickness limits, then impedance between power supply and ground is reduced, but the distance between power supply layer and ground layer is limited and further capacitance increase becomes difficult
Solution Approach 1:
The invention transitions from increasing capacitance within the chip thickness dimension to increasing capacitance in the planar dimension by providing large-area power supply and ground conductor layers on the wiring board. This allows the capacitor to be formed in the horizontal plane rather than being constrained by vertical thickness, thereby achieving high capacitance without increasing chip stack height.
Solution Approach 2:
The invention introduces a wiring board as an intermediary structure that carries large-area power supply and ground conductor layers. This wiring board serves as a mediator between the chip and the external circuit, providing the necessary capacitance function without requiring increased chip thickness or additional chip layers.
2Reliability
If chip stack height is increased to accommodate larger distance between power supply and ground layers, then capacitance increases, but device size increases and downsizing objective is compromised
Solution Approach 1:
The invention resolves the conflict between capacitance and device size by moving the capacitance-generating structure from the vertical dimension (chip stack height) to the horizontal dimension (wiring board area). This allows high capacitance to be achieved without increasing the vertical profile or overall device volume, thereby maintaining the downsizing objective while improving high-frequency impedance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces voltage fluctuation noise and impedance between the power supply and ground, even at high frequencies, enhancing the operation characteristics and reliability of the semiconductor device while potentially reducing its size and cost by minimizing the need for external chip capacitors.
Implementation Method 1
the capacitance is increased by the ground conductor layer of the conductor-coated chip and the power supply conductor layer of the semiconductor chip
Data Source
AI summary
According to one embodiment, a semiconductor device includes a wiring board, a spacer board that is mounted on the wiring board and in which a power supply conductor layer and a ground conductor layer are provided, at least one first semiconductor chip that is mounted on the spacer board including a power supply layer electrically connected to the power supply conductor layer and a ground layer electrically connected to the ground conductor layer, and a second semiconductor chip that is mounted on the wiring board.