Semiconductor Structure with Dummy Spacer Removal for Capacitance Reduction
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Solution Overview
Problem
Current semiconductor structures face challenges in reducing effective capacitance between the gate structure and source/drain plugs due to the high dielectric constant of materials used, which hinders the miniaturization and performance enhancement of integrated circuits.
Innovation Solution
A method involving the formation of a semiconductor structure with a dummy spacer on the side wall of the gate structure, followed by the removal of the dummy spacer to create a gap, and the use of a top dielectric layer with a lower dielectric constant to fill the gap or form an air gap, thereby reducing the effective capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a dummy spacer is formed on the side wall of the gate structure to define the contact opening, then the manufacturing precision of the contact plug is improved, but the effective capacitance between the gate structure and source/drain plugs increases due to the high dielectric constant of the dummy spacer material
Solution Approach 1:
The patent extracts and removes the dummy spacer material after it has served its purpose as a mask for forming the contact opening. By removing the dummy spacer, the source of high dielectric constant interference is eliminated, thereby reducing the effective capacitance between the gate structure and source/drain plugs while maintaining the manufacturing precision benefits that the dummy spacer provided during fabrication
Solution Approach 2:
The patent changes the dielectric constant parameter of the material filling the gap between the gate structure and contact plug from high (dummy spacer material) to low (low-k dielectric material or air). This parameter change directly reduces the effective capacitance while the gap structure maintains the precise contact plug positioning that the dummy spacer originally provided
2Productivity
If the critical dimensions of components are reduced to increase circuit density, then the integrated level and performance are improved, but the wafer surface area available for routing lines becomes insufficient
Solution Approach 1:
The patent utilizes the vertical dimension by forming contact plugs that extend through the wafer thickness to connect different metal layers. This three-dimensional interconnect approach allows routing signals vertically through the substrate, thereby reducing the need for additional horizontal routing space on the wafer surface and enabling higher circuit density
3Ease of manufacture
If the gap between the contact etch stop layer and gate structure is filled with high-k dielectric material, then the manufacturing process is simplified, but the effective capacitance increases and performance deteriorates
Solution Approach 1:
The patent changes the dielectric constant parameter of the gap filling material from high-k to low-k. Although this requires an additional material deposition step, the significant reduction in effective capacitance achieved by using low-k or air-filled gaps outweighs the minor increase in process complexity, thereby improving device performance
Data Source
AI summary
A semiconductor structure and a forming method thereof are provided. The method includes: providing a substrate, a dummy spacer being formed on a side wall of the gate structure, a contact etch stop layer being formed on a side wall of the dummy spacer, and a source/drain doped area being formed in the substrate on two sides of the gate structure; forming a sacrificial dielectric layer above tops of the source/drain doped area and the gate structure; forming a source/drain plug running through the sacrificial dielectric layer; etching the sacrificial dielectric layer until a top of the dummy spacer is exposed; removing, after the top of the dummy spacer is exposed, the dummy spacer to form a gap between the contact etch stop layer and the side wall of the gate structure; and forming a top dielectric layer filling between the source/drain plugs.