Semiconductor Spacer Double Patterning for Sub-50nm Feature Density
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Solution Overview
Problem
Conventional semiconductor lithography technologies face challenges in achieving smaller feature sizes due to wavelength limitations and the need for extreme precision, particularly in sub-wavelength or low-k1 applications, where optical proximity effects and non-linear imaging behaviors complicate the creation of complex patterns, and current double patterning techniques are not efficient for arbitrary patterns beyond simple lines.
Innovation Solution
The method involves using spacer double patterning to create lines and components on a semiconductor device without an additional mask layer, where a sacrificial layer and spacer material are deposited and etched to form patterns with varying widths, allowing for the creation of features and components in the same mask layer, such as contact pads and logic devices, by manipulating the spacer material's width and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography with DUV light is used, then manufacturing process is simple, but minimum feature size is limited to approximately 50 nm
Solution Approach 1:
The patent divides the patterning process into multiple stages using spacer double patterning. First, a mandrel pattern is formed, then spacer material is deposited and etched to create additional patterns. This segmentation allows achieving sub-50nm features by breaking down the single-step lithography into multiple controlled steps, effectively circumventing the diffraction limit of DUV light.
Solution Approach 2:
The patent transitions from planar 2D patterning to 3D spacer formation. By depositing spacer material vertically on mandrels and using anisotropic etching to preserve vertical surfaces while removing horizontal surfaces, the process creates patterns in the vertical dimension that translate to enhanced horizontal resolution, enabling features below the conventional lithographic limit.
2Manufacturing precision
If additional mask layers are used to form components with different widths, then pattern precision is improved, but lithography steps and device complexity increase
Solution Approach 1:
The spacer material serves multiple functions: it defines line patterns, creates contact pads of different widths, and forms components with varying dimensions—all in a single spacer deposition and etch sequence. The anisotropic etching process universally applies to all mandrels regardless of their original dimensions, automatically creating the appropriate final pattern widths based on mandrel spacing and spacer thickness.
Solution Approach 2:
The patent combines the formation of lines and components with different width requirements into a single lithography step. By strategically placing mandrels at different spacings and using uniform spacer deposition, the process simultaneously creates narrow lines, wide contact pads, and intermediate features without requiring separate photomasks or lithography exposures.
3Productivity
If spacer material remains on horizontal surfaces, then pattern density is increased, but manufacturing precision deteriorates due to unwanted material presence
Solution Approach 1:
The patent employs periodic or cyclic processing steps: deposit spacer material, perform anisotropic etch to remove horizontal surfaces, then repeat the process for subsequent patterning layers. This periodic removal and redeposition cycle ensures that horizontal surfaces are consistently cleared of unwanted spacer material while preserving the intended vertical pattern structures, maintaining both density and precision across multiple patterning iterations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of lines and components with increased density and precision without the need for additional lithography steps, effectively addressing the limitations of conventional techniques by allowing for the creation of arbitrary patterns and enhancing feature density in semiconductor devices.
Implementation Method 1
etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces
Implementation Method 2
depositing spacer material over the first pattern on the substrate
Data Source
AI summary
Methods of semiconductor device fabrication are disclosed. An exemplary method includes processes of depositing a first pattern on a semiconductor substrate, wherein the first pattern defines wide and narrow spaces; depositing spacer material over the first pattern on the substrate; etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of a wide space defined by the first pattern and remains within narrow a space defined by the first pattern; and removing the first pattern from the substrate. In one embodiment, the first pattern can comprise sacrificial material, which can include, for example, polysilicon material. The deposition can comprise physical vapor deposition, chemical vapor deposition, electrochemical deposition, molecular beam epitaxy, atomic layer deposition or other deposition techniques. According to another embodiment, features for lines and logic device components having a width greater than that of the lines are formed in the spacer material in the same mask layer.