Semiconductor Spacer Layer Etch Resistance Control
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Solution Overview
Problem
In advanced semiconductor process nodes, such as 16 nanometer and beyond, the gate-last process for forming field effect transistors (FETs) faces issues like footing problems in dummy gate structures, leading to spacer thinning or breakage, and merged doped silicon features due to etching, causing device failures and manufacturing challenges.
Innovation Solution
A method involving the formation of a first spacer layer over a substrate and gate structures, followed by carbon implantation at a tilted angle to increase etch resistance, and subsequent germanium implantation to decrease etch resistance on top surfaces, allowing for controlled etching and preventing spacer breakdown and silicon feature merging, while maintaining spacer integrity during epitaxial growth and high-k metal gate stack formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a dummy gate structure is formed in a gate-last process, then the final gate stack can be fabricated last with reduced subsequent high temperature processing, but footing problems occur in the dummy gate structure leading to spacer thinning or breakage
Solution Approach 1:
The patent applies local quality by differentiating the etch resistance properties at different locations of the spacer layer. Carbon implantation is performed at a tilted angle to selectively enhance etch resistance primarily at the lower portions and sidewalls of the spacer, while germanium implantation is applied to the top surface to modify etch characteristics there. This localized modification of material properties resolves the footing problem by preventing excessive etching at the spacer base while maintaining appropriate etchability at the top surface for subsequent processing.
Solution Approach 2:
The patent changes the physical and chemical parameters of the spacer layer through ion implantation processes. By introducing carbon and germanium atoms into the spacer layer, the etch resistance parameter is modified in a controlled manner. The tilted angle carbon implantation specifically targets the lower regions to increase etch resistance, preventing spacer thinning and breakage during subsequent etching operations, thereby maintaining manufacturing precision throughout the gate-last process.
2Reliability
If carbon implantation is performed at a tilted angle to increase etch resistance, then spacer integrity is maintained during etching, but additional process steps are required
Solution Approach 1:
The patent applies preliminary action by performing carbon implantation at a tilted angle before the spacer etching step. This pre-treatment modifies the spacer layer's etch resistance in advance, ensuring that the spacer maintains its integrity during subsequent etching operations. By preparing the spacer layer beforehand with enhanced etch resistance at critical regions, the process prevents spacer breakdown without requiring additional corrective steps later, thus improving reliability while managing process complexity.
3Manufacturing precision
If germanium implantation is performed to decrease etch resistance on top surfaces, then controlled etching is enabled, but process complexity increases
Solution Approach 1:
The patent applies local quality by selectively modifying the top surface of the spacer layer with germanium implantation. This creates a localized region with reduced etch resistance precisely where controlled etching is needed, while the lower portions retain enhanced etch resistance from carbon implantation. This spatial differentiation of material properties enables precise control over the etching process, allowing different regions of the spacer to etch at different rates as required by the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality of semiconductor devices by maintaining spacer profile and thickness, preventing device failures from spacer breakdown and silicon feature merging, and ensuring accurate epitaxial growth and gate stack formation, thereby improving the reliability and performance of FETs.
Implementation Method 1
implanting carbon into the spacer layer at a first angle tilted away from a first direction that is perpendicular to a top surface of the substrate
Implementation Method 2
implanting germanium into the spacer layer at a second angle that is different from the first angle, resulting in a second portion of the spacer layer on a top surface of the gate structure
Data Source
AI summary
A method of forming a semiconductor device includes receiving a substrate with a gate structure and forming a spacer layer over the substrate and the gate structure. The method further includes implanting carbon into the spacer layer at an angle tilted away from a first direction perpendicular to a top surface of the substrate, which increases etch resistance of the spacer layer on sidewalls of the gate structure. The method optionally includes implanting germanium into the spacer layer at the first direction, which decreases etch resistance of the spacer layer overlaying the gate structure and the substrate. The method further includes etching the spacer layer to expose the gate structure, resulting in a first portion of the spacer layer on the sidewalls of the gate structure. Due to increased etch resistance, the first portion of the spacer layer maintains its profile and thickness in subsequent fabrication processes.