Semiconductor Spacer Etching for Scaled FinFET and GAA Structures
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes and improving their performance is exacerbated by the complexity of fabrication processes as feature sizes continue to decrease.
Innovation Solution
A semiconductor device structure is formed using double-patterning or multi-patterning processes to create FinFETs and gate all around (GAA) transistor structures, with specific material layers and etching processes to define source/drain structures and gate stacks, followed by a gate replacement process to enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process complexity increases and device reliability deteriorates
Solution Approach 1:
The fabrication process is divided into multiple discrete stages including forming first and second trenches at different depths, selective epitaxial growth in specific regions, and staged doping processes. This segmentation allows each step to be optimized independently, managing overall process complexity while enabling continued scaling.
Solution Approach 2:
Different regions of the semiconductor structure receive different treatments: merged regions undergo specific epitaxial growth and doping, while non-merged regions maintain original characteristics. This local differentiation allows tailored optimization for each region's functional requirements, improving device reliability at scaled dimensions.
2Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but device reliability deteriorates
Solution Approach 1:
The structure incorporates merged regions with different depth trenches and selective epitaxial growth before final device formation. These pre-formed structures provide mechanical support and electrical isolation that cushion against reliability issues that would otherwise arise at scaled dimensions, enabling continued production efficiency gains.
Solution Approach 2:
Selective epitaxial regions act as intermediary structures between the shallow and deep trenches, providing gradual transition zones that maintain electrical integrity while enabling continued scaling. These intermediary regions prevent direct exposure of critical interfaces that would compromise device reliability.
3Device complexity
If conventional single-patterning processes are used, then fabrication process complexity remains low, but manufacturing precision deteriorates at smaller feature sizes
Solution Approach 1:
The patterning is divided into multiple stages with separate trench formation, epitaxial growth, and doping steps. Each stage achieves specific dimensional precision requirements, allowing overall manufacturing precision to be maintained even as feature sizes decrease, while managing process complexity through modular segmentation.
Solution Approach 2:
Trenches are formed to different depths in advance before epitaxial growth and doping operations. This preliminary structuring establishes precise geometric boundaries that guide subsequent processing steps, ensuring manufacturing precision is achieved before final device assembly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the yield and performance of semiconductor devices by enlarging contact structures, reducing contact resistance, maintaining capacitance, and allowing for device scaling while maintaining process compatibility and reducing costs.
Implementation Method 1
A spacer structure is formed over a sidewall of the gate stack
Implementation Method 2
portions of the spacer structure are removed to expose a top surface of the substrate
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The method includes forming a spacer structure over a sidewall of the gate stack. The method includes forming a source/drain structure in and over the substrate, wherein a portion of the spacer structure is between the source/drain structure and the gate stack. The method includes partially removing the outer layer, wherein a first lower portion of the outer layer remains between the source/drain structure and the gate stack. The method includes partially removing the middle layer, wherein a second lower portion of the middle layer remains between the source/drain structure and the gate stack.