Semiconductor Fine Pattern Formation via Spacer Etching
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Solution Overview
Problem
Conventional photolithography processes struggle to form fine and broad patterns simultaneously, leading to misalignment and increased manufacturing costs due to the need for separate processes and additional steps for high-density and low-density regions in semiconductor devices.
Innovation Solution
A method that involves providing a feature layer on a substrate, applying a mask layer, and using a spacer layer to etch the mask layer and feature layer simultaneously in different regions, allowing for the formation of fine and broad patterns in the same process step, thereby eliminating misalignment and reducing the number of photolithography steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional photolithography processes are used to pattern both fine and broad features, then the process is simple and cost-effective, but misalignment occurs between fine and broad patterns due to separate patterning steps
Solution Approach 1:
The patent merges the patterning of fine features and broad features into a single simultaneous etching step. The mold mask pattern serves as a unified mask structure that defines both fine patterns (through spacer formation) and broad patterns (through direct etching) in the same process step, eliminating the need for separate patterning operations and ensuring perfect alignment between different feature types.
Solution Approach 2:
The patent segments the mask layer into different functional regions: a mold mask pattern region that undergoes spacer formation for fine features, and a mask layer region that is directly etched for broad features. This segmentation allows each region to be processed according to its specific requirements while being formed in a single unified process step.
2Manufacturing precision
If separate photolithography processes are used for fine and broad patterns, then each pattern type can be optimized independently, but manufacturing costs increase due to additional process steps
Solution Approach 1:
The patent combines the patterning operations for fine and broad features into a single simultaneous etching process. The mold mask pattern and mask layer are etched at the same time using the same etching conditions, reducing the total number of process steps while maintaining the ability to control dimensions of both feature types through the unified mask structure.
3Manufacturing precision
If conventional photolithography is used for fine patterns, then the process is straightforward, but resolution limitations prevent formation of sufficiently fine pitch patterns
Solution Approach 1:
The patent performs preliminary action by forming the mold mask pattern first, then using it as a template to deposit spacers that define the fine feature dimensions. This preliminary mold mask structure enables the formation of fine pitch patterns that exceed the resolution capabilities of conventional photolithography, as the actual fine patterns are defined by the spacer thickness rather than direct photolithographic exposure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces costs, and ensures more reliable production of semiconductor devices with fine and broad patterns without misalignment, enhancing the efficiency and reliability of the manufacturing process.
Implementation Method 1
The spacer layer is anisotropically etched to form spacers at sidewalls of the structures. The resulting dimensions of the spacers can be accurately controlled by controlling the etch parameters.
Implementation Method 2
performing an etching process to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region
Data Source
AI summary
In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.