Semiconductor Spacer Etching Using Fluorine Helium Gas
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Solution Overview
Problem
Conventional spacer etching techniques using silicon oxide and silicon nitride react with high K dielectric materials, leading to increased Effective Oxide Thickness (EOT) and degraded gate control capability, especially in advanced logic devices with metal gate configurations, causing damage to substrates and uniformity issues.
Innovation Solution
A method involving a gate stack formation with a dielectric layer of silicon nitride, using fluorine-based and helium-based gases for main and over etching operations without a silicon oxide etching stop layer, optimizing electrode power, chamber pressure, and gas flow rates to achieve a steep spacer profile and high selectivity, reducing substrate damage and EOT.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching techniques using silicon oxide and silicon nitride are employed, then the etching process can be performed, but the high K dielectric material reacts with silicon nitride resulting in increased EOT and degraded gate control capability
Solution Approach 1:
The patent removes the silicon oxide etching stop layer from the conventional process stack. By extracting this layer, the process eliminates the reaction between silicon nitride and high K dielectric materials, preventing EOT increase and maintaining gate control capability in advanced logic devices with metal gate configurations
Solution Approach 2:
The patent changes the etching process parameters by using optimized electrode power, chamber pressure, and gas flow rates with fluorine-based and helium-based gases. This enables selective removal of silicon nitride without requiring a silicon oxide stop layer, achieving high selectivity (>10:1) while preventing harmful reactions with high K dielectric materials
2Productivity
If Ar-based gases are used for spacer etching, then the etching process can proceed, but substrate damage occurs particularly in nanometer-scale devices
Solution Approach 1:
The patent replaces Ar-based etching gases with fluorine-based and helium-based gases. This parameter change maintains adequate etching rates while significantly reducing substrate damage, especially for nanometer-scale devices. The optimized gas composition and process parameters achieve high selectivity (>10:1) without compromising device integrity
Solution Approach 2:
The patent uses consumable etching gases (fluorine-based and helium-based) that can be easily replenished. These gases provide the necessary etching capability while minimizing harmful effects on the substrate, allowing for precise control of the etching process without long-term damage accumulation
3Manufacturing precision
If the etching rate is slowed down to improve uniformity, then repeatability and reliability improve, but the etching process becomes less efficient
Solution Approach 1:
The patent optimizes multiple process parameters simultaneously: electrode power, chamber pressure, and gas flow rates. This multi-parameter optimization enables uniform etching across the substrate while maintaining high etching efficiency. The fluorine-based and helium-based gas combination provides consistent etching rates without requiring excessively slow processing
Solution Approach 2:
The patent implements endpoint detection and process monitoring to ensure uniform etching. By detecting when the etching reaches the desired depth and adjusting parameters accordingly, the process maintains high uniformity and repeatability while avoiding unnecessary延长 of the etching time, thus preserving productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces substrate damage, enhances gate control capability, and improves driving current by optimizing the etching process, achieving a high selectivity greater than 10:1 and reducing the Effective Oxide Thickness, thus addressing the challenges of scaling down in semiconductor manufacturing.
Implementation Method 1
performing a main etching operation on the dielectric layer to form a spacer
Implementation Method 2
the main etching operation and/or the over etching operation may adopt etching gases including a fluorine-based gas
Implementation Method 3
the main etching operation and/or the over etching operation may adopt etching gases including a fluorine-based gas, an oxidizing gas and a helium-based gas
Implementation Method 4
the main etching operation and/or the over etching operation may adopt etching gases including a fluorine-based gas, an oxidizing gas and a helium-based gas
Data Source
AI summary
A method of manufacturing a semiconductor device is disclosed. The method may comprise: forming a gate stack on a substrate; depositing a dielectric layer on the substrate and the gate stack; performing a main etching operation on the dielectric layer to form a spacer, with a remainder of the dielectric layer left on the substrate; and performing an over etching operation to remove the remainder of the dielectric layer. According to the method disclosed herein, two etching operations where an etching gas comprises a helium gas are performed, without forming an etching stop layer of silicon oxide. As a result, it is possible to reduce damages to the substrate and also to reduce the process complexity. Further, it is possible to optimize a threshold voltage, effectively reduce an EOT, and enhance a gate control capability and a driving current.