Semiconductor Device Fine Metal Patterning Using Spacer Etching
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Solution Overview
Problem
The increasing demand for high integration and high-speed semiconductor devices poses challenges in manufacturing fine metal patterns without process defects, particularly due to reduced process margins in exposure processes and the risk of distorted patterns caused by using a single photomask for multiple conductive patterns.
Innovation Solution
A method involving multiple photomasks and a spacer layer is used to form highly-integrated fine metal patterns, where the spacer layer is anisotropically etched to create self-aligned openings, allowing for precise patterning and increased spacing between conductive patterns, thereby preventing distortion and electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single photomask is used to define multiple conductive patterns, then device complexity is reduced, but manufacturing precision deteriorates due to pattern distortion
Solution Approach 1:
The patent divides the patterning process into multiple stages using separate photomasks for different conductive patterns. Instead of attempting to define all conductive patterns in a single exposure, the method segments the process so that first and second conductive patterns are defined by different photomasks, eliminating mutual interference and distortion while maintaining overall device complexity at acceptable levels
Solution Approach 2:
The patent introduces a vertical dimension to the patterning process by forming mold patterns at different heights and using spacer layers to define subsequent patterns. This multi-layer approach allows different conductive patterns to be defined in different vertical planes, enabling precise positioning without the distortion that occurs when all patterns are defined in a single horizontal plane
2Area of moving object
If exposure process margins are reduced to achieve finer patterns, then integration density is improved, but manufacturing precision deteriorates due to process defects
Solution Approach 1:
The patent introduces mold patterns and spacer layers as intermediary structures that facilitate the formation of fine conductive patterns. Instead of directly exposing the conductive pattern material at reduced margins, the process uses mold patterns formed by photomasks and spacer layers formed by CVD as intermediate steps, providing process buffers that maintain manufacturing precision even when targeting finer final pattern dimensions
Solution Approach 2:
The patent performs preliminary patterning actions by forming mold patterns and spacer layers before final conductive pattern formation. These preliminary structures are created with adequate process margins, and then used as templates to define the final fine-pitch conductive patterns, ensuring that the critical dimensions are established when process control is most effective
3Reliability
If spacing between conductive patterns is increased to prevent electrical shorts, then reliability is improved, but integration density deteriorates
Solution Approach 1:
The patent resolves the spacing contradiction by transitioning to three-dimensional patterning. Mold patterns are formed at different heights, and spacer layers are deposited conformally to create vertically-staggered conductive patterns. This vertical separation allows conductive patterns to be positioned closer together in the horizontal plane while maintaining adequate electrical isolation through the vertical dimension, thereby improving integration density without compromising reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of highly-integrated semiconductor devices with precise conductive patterns, reducing the risk of process defects and ensuring accurate pattern formation, thus enhancing manufacturing efficiency and device performance.
Implementation Method 1
forming a spacer pattern by anisotropically etching the portion of the spacer layer exposed by the first opening until a portion of a top surface of the hardmask layer is exposed
Data Source
AI summary
A method of manufacturing a semiconductor device may include forming a hardmask layer on a substrate, forming a first mold pattern on the hardmask layer using a first photolithography process, conformally forming a spacer layer on the first mold pattern and on portions of the hardmask layer exposed by the first mold pattern, forming a first mold layer using a second photolithography process. The first mold layer may have a first opening that exposes a portion of the spacer layer. The method may include forming a spacer pattern by anisotropically etching the portion of the spacer layer exposed by the first opening until a portion of a top surface of the hardmask layer is exposed, and using the spacer pattern as an etching mask to pattern the hardmask layer.