Semiconductor Spacer Formation for Threshold Voltage Uniformity
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Solution Overview
Problem
The challenge in semiconductor device development is achieving higher integration levels while maintaining reliability and preventing non-uniformity of threshold voltages, which is complicated by the need for advanced exposure techniques and the difficulty in achieving precise pattern widths and spacings.
Innovation Solution
A method involving the sequential formation of spacers on a gate electrode, etching to create a recess region with a compressive stress pattern, and using a protective spacer to fill the gap between spacers, along with thermal or plasma treating processes, to enhance semiconductor device reliability and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If new exposure techniques are used to achieve higher integration levels, then pattern precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent segments the spacer formation process into multiple sequential steps (first spacer, second spacer, third spacer) with different materials and functions. This segmentation allows each spacer to serve specific purposes in controlling pattern dimensions and stress distribution, achieving precise pattern formation without requiring advanced exposure techniques.
Solution Approach 2:
The patent applies local quality by using different materials for different spacers (silicon nitride for first and third spacers, silicon oxide for second spacer) and forming a protective spacer only in specific gap regions. This localized material selection optimizes etch selectivity and stress control in specific areas, improving pattern precision while simplifying the overall manufacturing process.
2Manufacturing precision
If multiple spacers are formed sequentially to control pattern dimensions, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The second spacer made of silicon oxide serves as an intermediary layer between the first and third spacers. This intermediary spacer with different etch selectivity enables selective removal of the lower portion of the second spacer to form gap regions, while protecting the first and third spacers. This intermediary structure simplifies the overall process by providing a controlled method to create protective spacer regions without additional complex steps.
Solution Approach 2:
The patent utilizes parameter changes in material properties, specifically etch selectivity, to simplify the formation process. By selecting materials with distinct etch selectivities (silicon nitride vs. silicon oxide), the process enables selective etching to form gap regions and protective spacers automatically, reducing the need for additional masking and patterning steps.
3Reliability
If gap regions are formed between spacers to apply compressive stress, then carrier mobility is improved, but structural stability may be compromised
Solution Approach 1:
The patent applies beforehand cushioning by forming protective spacers in the gap regions before removing the lower portion of the second spacer. These protective spacers act as cushioning structures that maintain structural integrity during subsequent processing steps, preventing collapse or deformation of the spacer system while allowing compressive stress to be applied to the semiconductor substrate in the gap regions.
Solution Approach 2:
The patent uses composite materials strategy by combining silicon nitride (first and third spacers) with silicon oxide (second spacer and protective spacers) in a multi-layer structure. This composite structure provides both the mechanical stability needed to maintain spacer integrity and the selective etchability required to form gap regions for stress application, achieving both structural stability and improved carrier mobility.
Data Source
AI summary
According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.