Semiconductor Spacer Structure for Self-Aligned Gate Isolation

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Solution Overview

Problem

As integrated circuits shrink, the distance between self-aligned contact structures and gate structures decreases, leading to increased leakage current due to short circuits, and traditional spacer structures are often thinned during formation, failing to effectively isolate these components.

Innovation Solution

A method is developed to form a spacer structure with an approximately vertical profile by using self-aligned hard mask patterns to minimize thickness loss during etching, thereby reducing the exposure of gate structure shoulders and improving isolation, using a multi-layer spacer material and selective etching processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional spacer structure formation is used, then the process is simple, but the spacer thickness is lost during etching removal, causing incomplete isolation

Engineering Contradiction:
Improveisolation effectivenessVSAvoidspacer thickness retention
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The spacer structure is divided into multiple segments: a first spacer layer, a second spacer layer, and a third spacer layer with different materials and functions. This segmentation allows each layer to be optimized independently - the first layer provides base isolation, the second layer maintains thickness during etching, and the third layer ensures complete isolation, thereby resolving the contradiction between isolation effectiveness and thickness retention.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses composite materials with different etching selectivities for the spacer layers. The first spacer layer uses a material with high etching selectivity that protects the second layer during removal, while the second layer uses a material with low etching selectivity that maintains its thickness. This composite material approach enables differential etching that preserves spacer thickness while achieving complete isolation.

Inventive Principle:
Principle #40Composite materials

2Reliability

If spacer thickness is reduced to improve isolation, then isolation improves, but the gate structure shoulders become exposed, causing leakage current

Engineering Contradiction:
Improveisolation effectivenessVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies beforehand cushioning by designing the first spacer layer with sufficient thickness and high etching selectivity to cushion and protect the second spacer layer during the etching removal process. This ensures that the second layer maintains its thickness and continues to provide effective isolation, preventing gate structure shoulder exposure and leakage current while still achieving complete isolation between components.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If complete removal of spacer material is performed, then isolation is improved, but manufacturing complexity increases due to multiple etching steps

Engineering Contradiction:
Improveisolation effectivenessVSAvoidetching process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by utilizing the different etching selectivity parameters of the three spacer layer materials. The first and third layers have high etching selectivity, allowing them to be removed completely, while the second layer has low etching selectivity, allowing it to be preserved. This parameter-based differentiation enables complete isolation through selective removal without requiring overly complex multi-step etching processes.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250300017A1Method for forming semiconductor structure
Publication Date: 2025.09.25 WINBOND ELECTRONICS CORP
  • US20250300017A1 patent drawing
  • US20250300017A1 patent drawing
  • US20250300017A1 patent drawing

AI summary

A method for forming a semiconductor structure, comprising: forming a stacked structure on a substrate, the stacked structure including a cap structure including first and second cap layers of different materials; sequentially forming first and second spacer material layers on the substrate and the stacked structure; removing a first portion of the second spacer material layer and a first portion of the first spacer material layer to expose the second cap layer; removing a second portion of the second spacer material layer, so that a portion of the second cap layer protrudes from the second spacer material layer; forming a hard mask pattern self-aligned with the portion of the second cap layer; and using the hard mask pattern as a mask, removing a third portion of the second spacer material layer to form a spacer structure on the sidewall of the stacked structure.