Semiconductor Patterning via Spacer Height Differential
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Solution Overview
Problem
Conventional photolithography processes fail to meet the design rules for very small elements in semiconductor devices due to increased integration, necessitating the development of methods for forming fine and large patterns effectively.
Innovation Solution
The method involves forming a hard mask layer on an etch target layer with specific regions, creating preliminary mask patterns, spacer layers, and using these structures as etching masks to achieve the desired pattern sizes through a series of etching and spacer formation steps, allowing for both fine and large pattern formation in semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography processes are used, then the manufacturing process is simple, but the manufacturing precision cannot meet the design rule for very small elements
Solution Approach 1:
The patent applies segmentation by dividing the pattern formation process into multiple stages: first forming preliminary mask patterns, then forming spacers on sidewalls, and finally forming final patterns through sequential etching. This multi-stage approach enables precise control of pattern dimensions that cannot be achieved with conventional single-step photolithography, directly resolving the contradiction between manufacturing precision and process complexity.
Solution Approach 2:
The patent introduces a vertical dimension by forming spacer layers on the sidewalls of preliminary mask patterns. This three-dimensional approach allows the pattern dimensions to be controlled not only by lateral photolithography but also by vertical spacer thickness, thereby achieving higher precision in pattern formation while managing process complexity through dimensional expansion.
2Manufacturing precision
If double patterning technology is used to form fine patterns, then the manufacturing precision improves, but the process complexity increases
Solution Approach 1:
The patent employs preliminary action by first forming preliminary mask patterns that serve as templates for subsequent spacer formation. These preliminary structures are prepared in advance to define the locations where spacers will be formed, enabling precise control of final pattern dimensions. This preliminary structuring reduces the complexity of later etching steps by pre-establishing the pattern framework.
Solution Approach 2:
The spacer layer acts as an intermediary between the preliminary mask patterns and the final pattern structures. By forming spacers on the sidewalls of preliminary masks and then selectively removing the preliminary masks, the patent creates final patterns with precision controlled by spacer thickness rather than direct photolithography, thereby improving manufacturing precision while managing process complexity through the intermediary spacer formation step.
3Manufacturing precision
If quadruple patterning technology is used, then the manufacturing precision for very small elements is achieved, but the productivity decreases
Solution Approach 1:
The patent merges multiple patterning operations into a unified process flow where preliminary mask formation, spacer formation, and selective removal are integrated into sequential steps. By combining these operations and using the same spacer material and etching processes for both fine and large pattern regions, the patent achieves very small element precision while improving productivity compared to separate quadruple patterning processes for different pattern sizes.
Solution Approach 2:
The patent applies universality by using the same spacer formation process and etching methodology for both fine pattern regions and large pattern regions. The spacer layer serves multiple functions: defining fine pattern dimensions, protecting large pattern regions during selective etching, and enabling both pattern types to be formed through a unified process flow. This multi-functionality achieves very small element precision while maintaining productivity by avoiding separate specialized processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor devices with both fine and large patterns of varying sizes, providing a process margin and controlling the height difference between mask patterns, thus addressing the limitations of conventional photolithography.
Implementation Method 1
A spacer layer may be formed on a first sidewall and a first upper surface of the first preliminary mask pattern structure, and on a second sidewall and a second upper surface of the second preliminary mask pattern structure
Implementation Method 2
The hard mask layer may be partially removed using the first and second spacers and the second preliminary mask pattern structure as an etching mask to form first and second mask pattern structures
Data Source
AI summary
A method of forming fine patterns of semiconductor devices is disclosed. The method comprises forming a hard mask layer on an etch target, which includes first and second regions. The hard mask layer may further have first and second preliminary mask patterns formed on the same. Furthermore, a spacer layer may be formed on the first and second preliminary mask patterns. The spacer layer and the first and second preliminary mask patterns may be partially removed to form first and second spacers on sidewalls of the first and second preliminary mask patterns, respectively. The second spacer in the second region may have a top surface higher than a top surface of the first spacer in the first region. The height differences between the spacers allow forming of first and second patterns in the first and second regions, and thereby forming fine patterns of semiconductor devices.