Semiconductor Spacer Height Uniformity via Planarized Etching Selectivity
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Solution Overview
Problem
In semiconductor manufacturing, forming transistors with uniform assisting and selective gates is challenging due to misalignment and non-uniformity issues during the fabrication process, leading to asymmetry and varying heights of these gates.
Innovation Solution
A semiconductor process that uses organic materials to fill gaps beside spacers, ensuring they are pulled down to a uniform height by applying a material with a flat top surface and matching etching selectivity, allowing for the formation of assisting and selective gates with uniform heights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional spacer formation methods are used, then spacers can be formed on gates, but the spacers exhibit non-uniform heights and misalignment due to fabrication process variations
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer before spacer formation to pre-establish a flat surface. This preliminary step ensures that subsequent spacer deposition occurs on a uniform baseline, preventing height variations and misalignment issues that would otherwise require complex corrective processes later in fabrication.
Solution Approach 2:
The patent introduces a planarization layer as an intermediary element between the substrate/gate structures and the spacer material. This intermediary layer mediates the interface, providing a uniform foundation that eliminates surface irregularities and enables precise spacer formation without directly modifying the gate structures themselves.
2Manufacturing precision
If multiple process steps are used to achieve uniform gate heights, then manufacturing precision improves, but manufacturing time and cost increase
Solution Approach 1:
The patent merges the planarization function into the existing fabrication flow by combining surface flattening with the spacer formation process. Instead of treating planarization as a separate, time-consuming step, it is integrated with spacer deposition, allowing uniform gate heights to be achieved without adding significant manufacturing time or reducing throughput.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process simplifies the manufacturing flow, reduces costs, and ensures the integration of uniform gate structures, enhancing the integration of memory devices and logic units.
Implementation Method 1
The block, the spacer and the material are pulled down with the same pulling selectivity to the block, the spacer and the material
Data Source
AI summary
A semiconductor process includes the following steps. A first gate is formed on a substrate, wherein the first gate includes a stacked gate on the substrate and a cap on the stacked gate. A spacer material is formed to conformally cover the first gate and the substrate. The spacer material is etched to form a spacer on a side of the first gate and a block on the other side of the first gate corresponding to the side. A material covers the substrate, the block, the first gate and the spacer, wherein the top surface of the material is a flat surface. The block, the spacer and the material are pulled down with the same pulling selectivity so that an assisting gate is formed from the block and a selective gate is formed from the spacer.